1*d7b84ddcSIra Weiny /* 2*d7b84ddcSIra Weiny * QEMU CXL Events 3*d7b84ddcSIra Weiny * 4*d7b84ddcSIra Weiny * Copyright (c) 2022 Intel 5*d7b84ddcSIra Weiny * 6*d7b84ddcSIra Weiny * This work is licensed under the terms of the GNU GPL, version 2. See the 7*d7b84ddcSIra Weiny * COPYING file in the top-level directory. 8*d7b84ddcSIra Weiny */ 9*d7b84ddcSIra Weiny 10*d7b84ddcSIra Weiny #ifndef CXL_EVENTS_H 11*d7b84ddcSIra Weiny #define CXL_EVENTS_H 12*d7b84ddcSIra Weiny 13*d7b84ddcSIra Weiny /* 14*d7b84ddcSIra Weiny * CXL rev 3.0 section 8.2.9.2.2; Table 8-49 15*d7b84ddcSIra Weiny * 16*d7b84ddcSIra Weiny * Define these as the bit position for the event status register for ease of 17*d7b84ddcSIra Weiny * setting the status. 18*d7b84ddcSIra Weiny */ 19*d7b84ddcSIra Weiny typedef enum CXLEventLogType { 20*d7b84ddcSIra Weiny CXL_EVENT_TYPE_INFO = 0, 21*d7b84ddcSIra Weiny CXL_EVENT_TYPE_WARN = 1, 22*d7b84ddcSIra Weiny CXL_EVENT_TYPE_FAIL = 2, 23*d7b84ddcSIra Weiny CXL_EVENT_TYPE_FATAL = 3, 24*d7b84ddcSIra Weiny CXL_EVENT_TYPE_DYNAMIC_CAP = 4, 25*d7b84ddcSIra Weiny CXL_EVENT_TYPE_MAX 26*d7b84ddcSIra Weiny } CXLEventLogType; 27*d7b84ddcSIra Weiny 28*d7b84ddcSIra Weiny #endif /* CXL_EVENTS_H */ 29