1aa74e355SPeter Maydell /* 2aa74e355SPeter Maydell * ARM PrimeCell PL080/PL081 DMA controller 3aa74e355SPeter Maydell * 4aa74e355SPeter Maydell * Copyright (c) 2006 CodeSourcery. 5aa74e355SPeter Maydell * Copyright (c) 2018 Linaro Limited 6aa74e355SPeter Maydell * Written by Paul Brook, Peter Maydell 7aa74e355SPeter Maydell * 8aa74e355SPeter Maydell * This program is free software; you can redistribute it and/or modify 9aa74e355SPeter Maydell * it under the terms of the GNU General Public License version 2 or 10aa74e355SPeter Maydell * (at your option) any later version. 11aa74e355SPeter Maydell */ 12aa74e355SPeter Maydell 13*932a8d1fSPeter Maydell /* 14*932a8d1fSPeter Maydell * This is a model of the Arm PrimeCell PL080/PL081 DMA controller: 15aa74e355SPeter Maydell * The PL080 TRM is: 16*932a8d1fSPeter Maydell * https://developer.arm.com/documentation/ddi0196/latest 17aa74e355SPeter Maydell * and the PL081 TRM is: 18*932a8d1fSPeter Maydell * https://developer.arm.com/documentation/ddi0218/latest 19aa74e355SPeter Maydell * 20aa74e355SPeter Maydell * QEMU interface: 216d0ed6baSPeter Maydell * + sysbus IRQ 0: DMACINTR combined interrupt line 226d0ed6baSPeter Maydell * + sysbus IRQ 1: DMACINTERR error interrupt request 236d0ed6baSPeter Maydell * + sysbus IRQ 2: DMACINTTC count interrupt request 24aa74e355SPeter Maydell * + sysbus MMIO region 0: MemoryRegion for the device's registers 25112a829fSPeter Maydell * + QOM property "downstream": MemoryRegion defining where DMA 26112a829fSPeter Maydell * bus master transactions are made 27aa74e355SPeter Maydell */ 28aa74e355SPeter Maydell 29aa74e355SPeter Maydell #ifndef HW_DMA_PL080_H 30aa74e355SPeter Maydell #define HW_DMA_PL080_H 31aa74e355SPeter Maydell 32aa74e355SPeter Maydell #include "hw/sysbus.h" 33db1015e9SEduardo Habkost #include "qom/object.h" 34aa74e355SPeter Maydell 35aa74e355SPeter Maydell #define PL080_MAX_CHANNELS 8 36aa74e355SPeter Maydell 37aa74e355SPeter Maydell typedef struct { 38aa74e355SPeter Maydell uint32_t src; 39aa74e355SPeter Maydell uint32_t dest; 40aa74e355SPeter Maydell uint32_t lli; 41aa74e355SPeter Maydell uint32_t ctrl; 42aa74e355SPeter Maydell uint32_t conf; 43aa74e355SPeter Maydell } pl080_channel; 44aa74e355SPeter Maydell 45aa74e355SPeter Maydell #define TYPE_PL080 "pl080" 46aa74e355SPeter Maydell #define TYPE_PL081 "pl081" 478063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(PL080State, PL080) 48aa74e355SPeter Maydell 49db1015e9SEduardo Habkost struct PL080State { 50aa74e355SPeter Maydell SysBusDevice parent_obj; 51aa74e355SPeter Maydell 52aa74e355SPeter Maydell MemoryRegion iomem; 53aa74e355SPeter Maydell uint8_t tc_int; 54aa74e355SPeter Maydell uint8_t tc_mask; 55aa74e355SPeter Maydell uint8_t err_int; 56aa74e355SPeter Maydell uint8_t err_mask; 57aa74e355SPeter Maydell uint32_t conf; 58aa74e355SPeter Maydell uint32_t sync; 59aa74e355SPeter Maydell uint32_t req_single; 60aa74e355SPeter Maydell uint32_t req_burst; 61aa74e355SPeter Maydell pl080_channel chan[PL080_MAX_CHANNELS]; 62aa74e355SPeter Maydell int nchannels; 63aa74e355SPeter Maydell /* Flag to avoid recursive DMA invocations. */ 64aa74e355SPeter Maydell int running; 65aa74e355SPeter Maydell qemu_irq irq; 666d0ed6baSPeter Maydell qemu_irq interr; 676d0ed6baSPeter Maydell qemu_irq inttc; 68112a829fSPeter Maydell 69112a829fSPeter Maydell MemoryRegion *downstream; 70112a829fSPeter Maydell AddressSpace downstream_as; 71db1015e9SEduardo Habkost }; 72aa74e355SPeter Maydell 73aa74e355SPeter Maydell #endif 74