1 /* 2 * i.MX processors GPIO registers definition. 3 * 4 * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef IMX_GPIO_H 21 #define IMX_GPIO_H 22 23 #include "hw/sysbus.h" 24 #include "qom/object.h" 25 26 #define TYPE_IMX_GPIO "imx.gpio" 27 typedef struct IMXGPIOState IMXGPIOState; 28 #define IMX_GPIO(obj) OBJECT_CHECK(IMXGPIOState, (obj), TYPE_IMX_GPIO) 29 30 #define IMX_GPIO_MEM_SIZE 0x20 31 32 /* i.MX GPIO memory map */ 33 #define DR_ADDR 0x00 /* DATA REGISTER */ 34 #define GDIR_ADDR 0x04 /* DIRECTION REGISTER */ 35 #define PSR_ADDR 0x08 /* PAD STATUS REGISTER */ 36 #define ICR1_ADDR 0x0c /* INTERRUPT CONFIGURATION REGISTER 1 */ 37 #define ICR2_ADDR 0x10 /* INTERRUPT CONFIGURATION REGISTER 2 */ 38 #define IMR_ADDR 0x14 /* INTERRUPT MASK REGISTER */ 39 #define ISR_ADDR 0x18 /* INTERRUPT STATUS REGISTER */ 40 #define EDGE_SEL_ADDR 0x1c /* EDGE SEL REGISTER */ 41 42 #define IMX_GPIO_PIN_COUNT 32 43 44 struct IMXGPIOState { 45 /*< private >*/ 46 SysBusDevice parent_obj; 47 48 /*< public >*/ 49 MemoryRegion iomem; 50 51 uint32_t dr; 52 uint32_t gdir; 53 uint32_t psr; 54 uint64_t icr; 55 uint32_t imr; 56 uint32_t isr; 57 bool has_edge_sel; 58 uint32_t edge_sel; 59 bool has_upper_pin_irq; 60 61 qemu_irq irq[2]; 62 qemu_irq output[IMX_GPIO_PIN_COUNT]; 63 }; 64 65 #endif /* IMX_GPIO_H */ 66