1 /* 2 * ASPEED AST2400 I2C Controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21 #ifndef ASPEED_I2C_H 22 #define ASPEED_I2C_H 23 24 #include "hw/i2c/i2c.h" 25 #include "hw/sysbus.h" 26 #include "hw/registerfields.h" 27 #include "qom/object.h" 28 29 #define TYPE_ASPEED_I2C "aspeed.i2c" 30 #define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400" 31 #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500" 32 #define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600" 33 #define TYPE_ASPEED_1030_I2C TYPE_ASPEED_I2C "-ast1030" 34 OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C) 35 36 #define ASPEED_I2C_NR_BUSSES 16 37 #define ASPEED_I2C_MAX_POOL_SIZE 0x800 38 #define ASPEED_I2C_OLD_NUM_REG 11 39 #define ASPEED_I2C_NEW_NUM_REG 22 40 41 /* Tx State Machine */ 42 #define I2CD_TX_STATE_MASK 0xf 43 #define I2CD_IDLE 0x0 44 #define I2CD_MACTIVE 0x8 45 #define I2CD_MSTART 0x9 46 #define I2CD_MSTARTR 0xa 47 #define I2CD_MSTOP 0xb 48 #define I2CD_MTXD 0xc 49 #define I2CD_MRXACK 0xd 50 #define I2CD_MRXD 0xe 51 #define I2CD_MTXACK 0xf 52 #define I2CD_SWAIT 0x1 53 #define I2CD_SRXD 0x4 54 #define I2CD_STXACK 0x5 55 #define I2CD_STXD 0x6 56 #define I2CD_SRXACK 0x7 57 #define I2CD_RECOVER 0x3 58 59 /* I2C Global Register */ 60 REG32(I2C_CTRL_STATUS, 0x0) /* Device Interrupt Status */ 61 REG32(I2C_CTRL_ASSIGN, 0x8) /* Device Interrupt Target Assignment */ 62 REG32(I2C_CTRL_GLOBAL, 0xC) /* Global Control Register */ 63 FIELD(I2C_CTRL_GLOBAL, REG_MODE, 2, 1) 64 FIELD(I2C_CTRL_GLOBAL, SRAM_EN, 0, 1) 65 REG32(I2C_CTRL_NEW_CLK_DIVIDER, 0x10) /* New mode clock divider */ 66 67 /* I2C Old Mode Device (Bus) Register */ 68 REG32(I2CD_FUN_CTRL, 0x0) /* I2CD Function Control */ 69 FIELD(I2CD_FUN_CTRL, POOL_PAGE_SEL, 20, 3) /* AST2400 */ 70 SHARED_FIELD(M_SDA_LOCK_EN, 16, 1) 71 SHARED_FIELD(MULTI_MASTER_DIS, 15, 1) 72 SHARED_FIELD(M_SCL_DRIVE_EN, 14, 1) 73 SHARED_FIELD(MSB_STS, 9, 1) 74 SHARED_FIELD(SDA_DRIVE_IT_EN, 8, 1) 75 SHARED_FIELD(M_SDA_DRIVE_IT_EN, 7, 1) 76 SHARED_FIELD(M_HIGH_SPEED_EN, 6, 1) 77 SHARED_FIELD(DEF_ADDR_EN, 5, 1) 78 SHARED_FIELD(DEF_ALERT_EN, 4, 1) 79 SHARED_FIELD(DEF_ARP_EN, 3, 1) 80 SHARED_FIELD(DEF_GCALL_EN, 2, 1) 81 SHARED_FIELD(SLAVE_EN, 1, 1) 82 SHARED_FIELD(MASTER_EN, 0, 1) 83 REG32(I2CD_AC_TIMING1, 0x04) /* Clock and AC Timing Control #1 */ 84 REG32(I2CD_AC_TIMING2, 0x08) /* Clock and AC Timing Control #2 */ 85 REG32(I2CD_INTR_CTRL, 0x0C) /* I2CD Interrupt Control */ 86 REG32(I2CD_INTR_STS, 0x10) /* I2CD Interrupt Status */ 87 SHARED_FIELD(SLAVE_ADDR_MATCH, 31, 1) /* 0: addr1 1: addr2 */ 88 SHARED_FIELD(SLAVE_ADDR_RX_PENDING, 29, 1) 89 SHARED_FIELD(SLAVE_INACTIVE_TIMEOUT, 15, 1) 90 SHARED_FIELD(SDA_DL_TIMEOUT, 14, 1) 91 SHARED_FIELD(BUS_RECOVER_DONE, 13, 1) 92 SHARED_FIELD(SMBUS_ALERT, 12, 1) /* Bus [0-3] only */ 93 FIELD(I2CD_INTR_STS, SMBUS_ARP_ADDR, 11, 1) /* Removed */ 94 FIELD(I2CD_INTR_STS, SMBUS_DEV_ALERT_ADDR, 10, 1) /* Removed */ 95 FIELD(I2CD_INTR_STS, SMBUS_DEF_ADDR, 9, 1) /* Removed */ 96 FIELD(I2CD_INTR_STS, GCALL_ADDR, 8, 1) /* Removed */ 97 FIELD(I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 7, 1) /* use RX_DONE */ 98 SHARED_FIELD(SCL_TIMEOUT, 6, 1) 99 SHARED_FIELD(ABNORMAL, 5, 1) 100 SHARED_FIELD(NORMAL_STOP, 4, 1) 101 SHARED_FIELD(ARBIT_LOSS, 3, 1) 102 SHARED_FIELD(RX_DONE, 2, 1) 103 SHARED_FIELD(TX_NAK, 1, 1) 104 SHARED_FIELD(TX_ACK, 0, 1) 105 REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */ 106 SHARED_FIELD(SDA_OE, 28, 1) 107 SHARED_FIELD(SDA_O, 27, 1) 108 SHARED_FIELD(SCL_OE, 26, 1) 109 SHARED_FIELD(SCL_O, 25, 1) 110 SHARED_FIELD(TX_TIMING, 23, 2) 111 SHARED_FIELD(TX_STATE, 19, 4) 112 SHARED_FIELD(SCL_LINE_STS, 18, 1) 113 SHARED_FIELD(SDA_LINE_STS, 17, 1) 114 SHARED_FIELD(BUS_BUSY_STS, 16, 1) 115 SHARED_FIELD(SDA_OE_OUT_DIR, 15, 1) 116 SHARED_FIELD(SDA_O_OUT_DIR, 14, 1) 117 SHARED_FIELD(SCL_OE_OUT_DIR, 13, 1) 118 SHARED_FIELD(SCL_O_OUT_DIR, 12, 1) 119 SHARED_FIELD(BUS_RECOVER_CMD_EN, 11, 1) 120 SHARED_FIELD(S_ALT_EN, 10, 1) 121 /* Command Bits */ 122 SHARED_FIELD(RX_DMA_EN, 9, 1) 123 SHARED_FIELD(TX_DMA_EN, 8, 1) 124 SHARED_FIELD(RX_BUFF_EN, 7, 1) 125 SHARED_FIELD(TX_BUFF_EN, 6, 1) 126 SHARED_FIELD(M_STOP_CMD, 5, 1) 127 SHARED_FIELD(M_S_RX_CMD_LAST, 4, 1) 128 SHARED_FIELD(M_RX_CMD, 3, 1) 129 SHARED_FIELD(S_TX_CMD, 2, 1) 130 SHARED_FIELD(M_TX_CMD, 1, 1) 131 SHARED_FIELD(M_START_CMD, 0, 1) 132 REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */ 133 REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */ 134 SHARED_FIELD(RX_COUNT, 24, 5) 135 SHARED_FIELD(RX_SIZE, 16, 5) 136 SHARED_FIELD(TX_COUNT, 9, 5) 137 FIELD(I2CD_POOL_CTRL, OFFSET, 2, 6) /* AST2400 */ 138 REG32(I2CD_BYTE_BUF, 0x20) /* Transmit/Receive Byte Buffer */ 139 SHARED_FIELD(RX_BUF, 8, 8) 140 SHARED_FIELD(TX_BUF, 0, 8) 141 REG32(I2CD_DMA_ADDR, 0x24) /* DMA Buffer Address */ 142 REG32(I2CD_DMA_LEN, 0x28) /* DMA Transfer Length < 4KB */ 143 144 /* I2C New Mode Device (Bus) Register */ 145 REG32(I2CC_FUN_CTRL, 0x0) 146 FIELD(I2CC_FUN_CTRL, RB_EARLY_DONE_EN, 22, 1) 147 FIELD(I2CC_FUN_CTRL, DMA_DIS_AUTO_RECOVER, 21, 1) 148 FIELD(I2CC_FUN_CTRL, S_SAVE_ADDR, 20, 1) 149 FIELD(I2CC_FUN_CTRL, M_PKT_RETRY_CNT, 18, 2) 150 /* 17:0 shared with I2CD_FUN_CTRL[17:0] */ 151 REG32(I2CC_AC_TIMING, 0x04) 152 REG32(I2CC_MS_TXRX_BYTE_BUF, 0x08) 153 /* 31:16 shared with I2CD_CMD[31:16] */ 154 /* 15:0 shared with I2CD_BYTE_BUF[15:0] */ 155 REG32(I2CC_POOL_CTRL, 0x0c) 156 /* 31:0 shared with I2CD_POOL_CTRL[31:0] */ 157 REG32(I2CM_INTR_CTRL, 0x10) 158 REG32(I2CM_INTR_STS, 0x14) 159 FIELD(I2CM_INTR_STS, PKT_STATE, 28, 4) 160 FIELD(I2CM_INTR_STS, PKT_CMD_TIMEOUT, 18, 1) 161 FIELD(I2CM_INTR_STS, PKT_CMD_FAIL, 17, 1) 162 FIELD(I2CM_INTR_STS, PKT_CMD_DONE, 16, 1) 163 FIELD(I2CM_INTR_STS, BUS_RECOVER_FAIL, 15, 1) 164 /* 14:0 shared with I2CD_INTR_STS[14:0] */ 165 REG32(I2CM_CMD, 0x18) 166 FIELD(I2CM_CMD, W1_CTRL, 31, 1) 167 FIELD(I2CM_CMD, PKT_DEV_ADDR, 24, 7) 168 FIELD(I2CM_CMD, HS_MASTER_MODE_LSB, 17, 3) 169 FIELD(I2CM_CMD, PKT_OP_EN, 16, 1) 170 /* 15:0 shared with I2CD_CMD[15:0] */ 171 REG32(I2CM_DMA_LEN, 0x1c) 172 FIELD(I2CM_DMA_LEN, RX_BUF_LEN_W1T, 31, 1) 173 FIELD(I2CM_DMA_LEN, RX_BUF_LEN, 16, 11) 174 FIELD(I2CM_DMA_LEN, TX_BUF_LEN_W1T, 15, 1) 175 FIELD(I2CM_DMA_LEN, TX_BUF_LEN, 0, 11) 176 REG32(I2CS_INTR_CTRL, 0x20) 177 REG32(I2CS_INTR_STS, 0x24) 178 /* 31:29 shared with I2CD_INTR_STS[31:29] */ 179 FIELD(I2CS_INTR_STS, SLAVE_PARKING_STS, 24, 2) 180 FIELD(I2CS_INTR_STS, SLAVE_ADDR3_NAK, 22, 1) 181 FIELD(I2CS_INTR_STS, SLAVE_ADDR2_NAK, 21, 1) 182 FIELD(I2CS_INTR_STS, SLAVE_ADDR1_NAK, 20, 1) 183 FIELD(I2CS_INTR_STS, SLAVE_ADDR_INDICATOR, 18, 2) 184 FIELD(I2CS_INTR_STS, PKT_CMD_FAIL, 17, 1) 185 FIELD(I2CS_INTR_STS, PKT_CMD_DONE, 16, 1) 186 /* 14:0 shared with I2CD_INTR_STS[14:0] */ 187 REG32(I2CS_CMD, 0x28) 188 FIELD(I2CS_CMD, W1_CTRL, 31, 1) 189 FIELD(I2CS_CMD, PKT_MODE_ACTIVE_ADDR, 17, 2) 190 FIELD(I2CS_CMD, PKT_MODE_EN, 16, 1) 191 FIELD(I2CS_CMD, AUTO_NAK_INACTIVE_ADDR, 15, 1) 192 FIELD(I2CS_CMD, AUTO_NAK_ACTIVE_ADDR, 14, 1) 193 /* 13:0 shared with I2CD_CMD[13:0] */ 194 REG32(I2CS_DMA_LEN, 0x2c) 195 FIELD(I2CS_DMA_LEN, RX_BUF_LEN_W1T, 31, 1) 196 FIELD(I2CS_DMA_LEN, RX_BUF_LEN, 16, 11) 197 FIELD(I2CS_DMA_LEN, TX_BUF_LEN_W1T, 15, 1) 198 FIELD(I2CS_DMA_LEN, TX_BUF_LEN, 0, 11) 199 REG32(I2CM_DMA_TX_ADDR, 0x30) 200 FIELD(I2CM_DMA_TX_ADDR, ADDR, 0, 31) 201 REG32(I2CM_DMA_RX_ADDR, 0x34) 202 FIELD(I2CM_DMA_RX_ADDR, ADDR, 0, 31) 203 REG32(I2CS_DMA_TX_ADDR, 0x38) 204 FIELD(I2CS_DMA_TX_ADDR, ADDR, 0, 31) 205 REG32(I2CS_DMA_RX_ADDR, 0x3c) 206 FIELD(I2CS_DMA_RX_ADDR, ADDR, 0, 31) 207 REG32(I2CS_DEV_ADDR, 0x40) 208 REG32(I2CM_DMA_LEN_STS, 0x48) 209 FIELD(I2CM_DMA_LEN_STS, RX_LEN, 16, 13) 210 FIELD(I2CM_DMA_LEN_STS, TX_LEN, 0, 13) 211 REG32(I2CS_DMA_LEN_STS, 0x4c) 212 FIELD(I2CS_DMA_LEN_STS, RX_LEN, 16, 13) 213 FIELD(I2CS_DMA_LEN_STS, TX_LEN, 0, 13) 214 REG32(I2CC_DMA_ADDR, 0x50) 215 REG32(I2CC_DMA_LEN, 0x54) 216 217 struct AspeedI2CState; 218 219 #define TYPE_ASPEED_I2C_BUS "aspeed.i2c.bus" 220 OBJECT_DECLARE_SIMPLE_TYPE(AspeedI2CBus, ASPEED_I2C_BUS) 221 struct AspeedI2CBus { 222 SysBusDevice parent_obj; 223 224 struct AspeedI2CState *controller; 225 226 MemoryRegion mr; 227 228 I2CBus *bus; 229 uint8_t id; 230 qemu_irq irq; 231 232 uint32_t regs[ASPEED_I2C_NEW_NUM_REG]; 233 }; 234 235 struct AspeedI2CState { 236 SysBusDevice parent_obj; 237 238 MemoryRegion iomem; 239 qemu_irq irq; 240 241 uint32_t intr_status; 242 uint32_t ctrl_global; 243 uint32_t new_clk_divider; 244 MemoryRegion pool_iomem; 245 uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE]; 246 247 AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES]; 248 MemoryRegion *dram_mr; 249 AddressSpace dram_as; 250 }; 251 252 253 struct AspeedI2CClass { 254 SysBusDeviceClass parent_class; 255 256 uint8_t num_busses; 257 uint8_t reg_size; 258 uint8_t gap; 259 qemu_irq (*bus_get_irq)(AspeedI2CBus *); 260 261 uint64_t pool_size; 262 hwaddr pool_base; 263 uint8_t *(*bus_pool_base)(AspeedI2CBus *); 264 bool check_sram; 265 bool has_dma; 266 267 }; 268 269 static inline bool aspeed_i2c_is_new_mode(AspeedI2CState *s) 270 { 271 return FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, REG_MODE); 272 } 273 274 static inline bool aspeed_i2c_bus_pkt_mode_en(AspeedI2CBus *bus) 275 { 276 if (aspeed_i2c_is_new_mode(bus->controller)) { 277 return ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_OP_EN); 278 } 279 return false; 280 } 281 282 static inline uint32_t aspeed_i2c_bus_ctrl_offset(AspeedI2CBus *bus) 283 { 284 if (aspeed_i2c_is_new_mode(bus->controller)) { 285 return R_I2CC_FUN_CTRL; 286 } 287 return R_I2CD_FUN_CTRL; 288 } 289 290 static inline uint32_t aspeed_i2c_bus_cmd_offset(AspeedI2CBus *bus) 291 { 292 if (aspeed_i2c_is_new_mode(bus->controller)) { 293 return R_I2CM_CMD; 294 } 295 return R_I2CD_CMD; 296 } 297 298 static inline uint32_t aspeed_i2c_bus_dev_addr_offset(AspeedI2CBus *bus) 299 { 300 if (aspeed_i2c_is_new_mode(bus->controller)) { 301 return R_I2CS_DEV_ADDR; 302 } 303 return R_I2CD_DEV_ADDR; 304 } 305 306 static inline uint32_t aspeed_i2c_bus_intr_ctrl_offset(AspeedI2CBus *bus) 307 { 308 if (aspeed_i2c_is_new_mode(bus->controller)) { 309 return R_I2CM_INTR_CTRL; 310 } 311 return R_I2CD_INTR_CTRL; 312 } 313 314 static inline uint32_t aspeed_i2c_bus_intr_sts_offset(AspeedI2CBus *bus) 315 { 316 if (aspeed_i2c_is_new_mode(bus->controller)) { 317 return R_I2CM_INTR_STS; 318 } 319 return R_I2CD_INTR_STS; 320 } 321 322 static inline uint32_t aspeed_i2c_bus_pool_ctrl_offset(AspeedI2CBus *bus) 323 { 324 if (aspeed_i2c_is_new_mode(bus->controller)) { 325 return R_I2CC_POOL_CTRL; 326 } 327 return R_I2CD_POOL_CTRL; 328 } 329 330 static inline uint32_t aspeed_i2c_bus_byte_buf_offset(AspeedI2CBus *bus) 331 { 332 if (aspeed_i2c_is_new_mode(bus->controller)) { 333 return R_I2CC_MS_TXRX_BYTE_BUF; 334 } 335 return R_I2CD_BYTE_BUF; 336 } 337 338 static inline uint32_t aspeed_i2c_bus_dma_len_offset(AspeedI2CBus *bus) 339 { 340 if (aspeed_i2c_is_new_mode(bus->controller)) { 341 return R_I2CC_DMA_LEN; 342 } 343 return R_I2CD_DMA_LEN; 344 } 345 346 static inline uint32_t aspeed_i2c_bus_dma_addr_offset(AspeedI2CBus *bus) 347 { 348 if (aspeed_i2c_is_new_mode(bus->controller)) { 349 return R_I2CC_DMA_ADDR; 350 } 351 return R_I2CD_DMA_ADDR; 352 } 353 354 static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus) 355 { 356 return SHARED_ARRAY_FIELD_EX32(bus->regs, aspeed_i2c_bus_ctrl_offset(bus), 357 MASTER_EN); 358 } 359 360 static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus) 361 { 362 uint32_t ctrl_reg = aspeed_i2c_bus_ctrl_offset(bus); 363 return SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, MASTER_EN) || 364 SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, SLAVE_EN); 365 } 366 367 I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr); 368 369 #endif /* ASPEED_I2C_H */ 370