1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu/notify.h" 5 #include "qapi/qapi-types-common.h" 6 #include "qemu/uuid.h" 7 #include "hw/boards.h" 8 #include "hw/block/fdc.h" 9 #include "hw/block/flash.h" 10 #include "hw/i386/x86.h" 11 12 #include "hw/hotplug.h" 13 #include "qom/object.h" 14 #include "hw/i386/sgx-epc.h" 15 #include "hw/cxl/cxl.h" 16 17 #define MAX_IDE_BUS 2 18 19 /** 20 * PCMachineState: 21 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling 22 * @boot_cpus: number of present VCPUs 23 */ 24 typedef struct PCMachineState { 25 /*< private >*/ 26 X86MachineState parent_obj; 27 28 /* <public> */ 29 30 /* State for other subsystems/APIs: */ 31 Notifier machine_done; 32 33 /* Pointers to devices and objects: */ 34 PCIBus *pcibus; 35 I2CBus *smbus; 36 PFlashCFI01 *flash[2]; 37 ISADevice *pcspk; 38 DeviceState *iommu; 39 BusState *idebus[MAX_IDE_BUS]; 40 41 /* Configuration options: */ 42 uint64_t max_ram_below_4g; 43 OnOffAuto vmport; 44 SmbiosEntryPointType smbios_entry_point_type; 45 const char *south_bridge; 46 47 bool acpi_build_enabled; 48 bool smbus_enabled; 49 bool sata_enabled; 50 bool hpet_enabled; 51 bool i8042_enabled; 52 bool default_bus_bypass_iommu; 53 bool fd_bootchk; 54 uint64_t max_fw_size; 55 56 /* ACPI Memory hotplug IO base address */ 57 hwaddr memhp_io_base; 58 59 SGXEPCState sgx_epc; 60 CXLState cxl_devices_state; 61 } PCMachineState; 62 63 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" 64 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" 65 #define PC_MACHINE_VMPORT "vmport" 66 #define PC_MACHINE_SMBUS "smbus" 67 #define PC_MACHINE_SATA "sata" 68 #define PC_MACHINE_I8042 "i8042" 69 #define PC_MACHINE_MAX_FW_SIZE "max-fw-size" 70 #define PC_MACHINE_SMBIOS_EP "smbios-entry-point-type" 71 72 /** 73 * PCMachineClass: 74 * 75 * Compat fields: 76 * 77 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by 78 * backend's alignment value if provided 79 * @acpi_data_size: Size of the chunk of memory at the top of RAM 80 * for the BIOS ACPI tables and other BIOS 81 * datastructures. 82 * @gigabyte_align: Make sure that guest addresses aligned at 83 * 1Gbyte boundaries get mapped to host 84 * addresses aligned at 1Gbyte boundaries. This 85 * way we can use 1GByte pages in the host. 86 * 87 */ 88 struct PCMachineClass { 89 /*< private >*/ 90 X86MachineClass parent_class; 91 92 /*< public >*/ 93 94 /* Device configuration: */ 95 bool pci_enabled; 96 const char *default_south_bridge; 97 98 /* Compat options: */ 99 100 /* Default CPU model version. See x86_cpu_set_default_version(). */ 101 int default_cpu_version; 102 103 /* ACPI compat: */ 104 bool has_acpi_build; 105 bool rsdp_in_ram; 106 int legacy_acpi_table_size; 107 unsigned acpi_data_size; 108 int pci_root_uid; 109 110 /* SMBIOS compat: */ 111 bool smbios_defaults; 112 bool smbios_legacy_mode; 113 bool smbios_uuid_encoded; 114 SmbiosEntryPointType default_smbios_ep_type; 115 116 /* RAM / address space compat: */ 117 bool gigabyte_align; 118 bool has_reserved_memory; 119 bool enforce_aligned_dimm; 120 bool broken_reserved_end; 121 bool enforce_amd_1tb_hole; 122 123 /* generate legacy CPU hotplug AML */ 124 bool legacy_cpu_hotplug; 125 126 /* use PVH to load kernels that support this feature */ 127 bool pvh_enabled; 128 129 /* create kvmclock device even when KVM PV features are not exposed */ 130 bool kvmclock_create_always; 131 132 /* resizable acpi blob compat */ 133 bool resizable_acpi_blob; 134 135 /* 136 * whether the machine type implements broken 32-bit address space bound 137 * check for memory. 138 */ 139 bool broken_32bit_mem_addr_check; 140 }; 141 142 #define TYPE_PC_MACHINE "generic-pc-machine" 143 OBJECT_DECLARE_TYPE(PCMachineState, PCMachineClass, PC_MACHINE) 144 145 /* ioapic.c */ 146 147 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled); 148 149 /* pc.c */ 150 151 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 152 153 #define PCI_HOST_PROP_RAM_MEM "ram-mem" 154 #define PCI_HOST_PROP_PCI_MEM "pci-mem" 155 #define PCI_HOST_PROP_SYSTEM_MEM "system-mem" 156 #define PCI_HOST_PROP_IO_MEM "io-mem" 157 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 158 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 159 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 160 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 161 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 162 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" 163 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" 164 #define PCI_HOST_PROP_SMM_RANGES "smm-ranges" 165 166 167 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 168 MemoryRegion *pci_address_space); 169 170 void xen_load_linux(PCMachineState *pcms); 171 void pc_memory_init(PCMachineState *pcms, 172 MemoryRegion *system_memory, 173 MemoryRegion *rom_memory, 174 uint64_t pci_hole64_size); 175 uint64_t pc_pci_hole64_start(void); 176 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 177 void pc_basic_device_init(struct PCMachineState *pcms, 178 ISABus *isa_bus, qemu_irq *gsi, 179 ISADevice *rtc_state, 180 bool create_fdctrl, 181 uint32_t hpet_irqs); 182 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus); 183 184 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs); 185 186 /* port92.c */ 187 #define PORT92_A20_LINE "a20" 188 189 #define TYPE_PORT92 "port92" 190 191 /* pc_sysfw.c */ 192 void pc_system_flash_create(PCMachineState *pcms); 193 void pc_system_flash_cleanup_unused(PCMachineState *pcms); 194 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); 195 bool pc_system_ovmf_table_find(const char *entry, uint8_t **data, 196 int *data_len); 197 void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, size_t flash_size); 198 199 /* sgx.c */ 200 void pc_machine_init_sgx_epc(PCMachineState *pcms); 201 202 extern GlobalProperty pc_compat_9_0[]; 203 extern const size_t pc_compat_9_0_len; 204 205 extern GlobalProperty pc_compat_8_2[]; 206 extern const size_t pc_compat_8_2_len; 207 208 extern GlobalProperty pc_compat_8_1[]; 209 extern const size_t pc_compat_8_1_len; 210 211 extern GlobalProperty pc_compat_8_0[]; 212 extern const size_t pc_compat_8_0_len; 213 214 extern GlobalProperty pc_compat_7_2[]; 215 extern const size_t pc_compat_7_2_len; 216 217 extern GlobalProperty pc_compat_7_1[]; 218 extern const size_t pc_compat_7_1_len; 219 220 extern GlobalProperty pc_compat_7_0[]; 221 extern const size_t pc_compat_7_0_len; 222 223 extern GlobalProperty pc_compat_6_2[]; 224 extern const size_t pc_compat_6_2_len; 225 226 extern GlobalProperty pc_compat_6_1[]; 227 extern const size_t pc_compat_6_1_len; 228 229 extern GlobalProperty pc_compat_6_0[]; 230 extern const size_t pc_compat_6_0_len; 231 232 extern GlobalProperty pc_compat_5_2[]; 233 extern const size_t pc_compat_5_2_len; 234 235 extern GlobalProperty pc_compat_5_1[]; 236 extern const size_t pc_compat_5_1_len; 237 238 extern GlobalProperty pc_compat_5_0[]; 239 extern const size_t pc_compat_5_0_len; 240 241 extern GlobalProperty pc_compat_4_2[]; 242 extern const size_t pc_compat_4_2_len; 243 244 extern GlobalProperty pc_compat_4_1[]; 245 extern const size_t pc_compat_4_1_len; 246 247 extern GlobalProperty pc_compat_4_0[]; 248 extern const size_t pc_compat_4_0_len; 249 250 extern GlobalProperty pc_compat_3_1[]; 251 extern const size_t pc_compat_3_1_len; 252 253 extern GlobalProperty pc_compat_3_0[]; 254 extern const size_t pc_compat_3_0_len; 255 256 extern GlobalProperty pc_compat_2_12[]; 257 extern const size_t pc_compat_2_12_len; 258 259 extern GlobalProperty pc_compat_2_11[]; 260 extern const size_t pc_compat_2_11_len; 261 262 extern GlobalProperty pc_compat_2_10[]; 263 extern const size_t pc_compat_2_10_len; 264 265 extern GlobalProperty pc_compat_2_9[]; 266 extern const size_t pc_compat_2_9_len; 267 268 extern GlobalProperty pc_compat_2_8[]; 269 extern const size_t pc_compat_2_8_len; 270 271 extern GlobalProperty pc_compat_2_7[]; 272 extern const size_t pc_compat_2_7_len; 273 274 extern GlobalProperty pc_compat_2_6[]; 275 extern const size_t pc_compat_2_6_len; 276 277 extern GlobalProperty pc_compat_2_5[]; 278 extern const size_t pc_compat_2_5_len; 279 280 extern GlobalProperty pc_compat_2_4[]; 281 extern const size_t pc_compat_2_4_len; 282 283 extern GlobalProperty pc_compat_2_3[]; 284 extern const size_t pc_compat_2_3_len; 285 286 extern GlobalProperty pc_compat_2_2[]; 287 extern const size_t pc_compat_2_2_len; 288 289 extern GlobalProperty pc_compat_2_1[]; 290 extern const size_t pc_compat_2_1_len; 291 292 extern GlobalProperty pc_compat_2_0[]; 293 extern const size_t pc_compat_2_0_len; 294 295 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ 296 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ 297 { \ 298 MachineClass *mc = MACHINE_CLASS(oc); \ 299 optsfn(mc); \ 300 mc->init = initfn; \ 301 } \ 302 static const TypeInfo pc_machine_type_##suffix = { \ 303 .name = namestr TYPE_MACHINE_SUFFIX, \ 304 .parent = TYPE_PC_MACHINE, \ 305 .class_init = pc_machine_##suffix##_class_init, \ 306 }; \ 307 static void pc_machine_init_##suffix(void) \ 308 { \ 309 type_register(&pc_machine_type_##suffix); \ 310 } \ 311 type_init(pc_machine_init_##suffix) 312 313 #endif 314