1 /* 2 * ARM GIC support 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Copyright (c) 2015 Huawei. 6 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 7 * Written by Peter Maydell 8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifndef HW_ARM_GICV3_COMMON_H 25 #define HW_ARM_GICV3_COMMON_H 26 27 #include "hw/sysbus.h" 28 #include "hw/intc/arm_gic_common.h" 29 30 /* 31 * Maximum number of possible interrupts, determined by the GIC architecture. 32 * Note that this does not include LPIs. When implemented, these should be 33 * dealt with separately. 34 */ 35 #define GICV3_MAXIRQ 1020 36 #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL) 37 38 /* Number of SGI target-list bits */ 39 #define GICV3_TARGETLIST_BITS 16 40 41 /* Minimum BPR for Secure, or when security not enabled */ 42 #define GIC_MIN_BPR 0 43 /* Minimum BPR for Nonsecure when security is enabled */ 44 #define GIC_MIN_BPR_NS (GIC_MIN_BPR + 1) 45 46 /* For some distributor fields we want to model the array of 32-bit 47 * register values which hold various bitmaps corresponding to enabled, 48 * pending, etc bits. These macros and functions facilitate that; the 49 * APIs are generally modelled on the generic bitmap.h functions 50 * (which are unsuitable here because they use 'unsigned long' as the 51 * underlying storage type, which is very awkward when you need to 52 * access the data as 32-bit values.) 53 * Each bitmap contains a bit for each interrupt. Although there is 54 * space for the PPIs and SGIs, those bits (the first 32) are never 55 * used as that state lives in the redistributor. The unused bits are 56 * provided purely so that interrupt X's state is always in bit X; this 57 * avoids bugs where we forget to subtract GIC_INTERNAL from an 58 * interrupt number. 59 */ 60 #define GICV3_BMP_SIZE (DIV_ROUND_UP(GICV3_MAXIRQ, 32)) 61 62 #define GIC_DECLARE_BITMAP(name) \ 63 uint32_t name[GICV3_BMP_SIZE] 64 65 #define GIC_BIT_MASK(nr) (1U << ((nr) % 32)) 66 #define GIC_BIT_WORD(nr) ((nr) / 32) 67 68 static inline void gic_bmp_set_bit(int nr, uint32_t *addr) 69 { 70 uint32_t mask = GIC_BIT_MASK(nr); 71 uint32_t *p = addr + GIC_BIT_WORD(nr); 72 73 *p |= mask; 74 } 75 76 static inline void gic_bmp_clear_bit(int nr, uint32_t *addr) 77 { 78 uint32_t mask = GIC_BIT_MASK(nr); 79 uint32_t *p = addr + GIC_BIT_WORD(nr); 80 81 *p &= ~mask; 82 } 83 84 static inline int gic_bmp_test_bit(int nr, const uint32_t *addr) 85 { 86 return 1U & (addr[GIC_BIT_WORD(nr)] >> (nr & 31)); 87 } 88 89 static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val) 90 { 91 uint32_t mask = GIC_BIT_MASK(nr); 92 uint32_t *p = addr + GIC_BIT_WORD(nr); 93 94 *p &= ~mask; 95 *p |= (val & 1U) << (nr % 32); 96 } 97 98 /* Return a pointer to the 32-bit word containing the specified bit. */ 99 static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr) 100 { 101 return addr + GIC_BIT_WORD(nr); 102 } 103 104 typedef struct GICv3State GICv3State; 105 typedef struct GICv3CPUState GICv3CPUState; 106 107 /* Some CPU interface registers come in three flavours: 108 * Group0, Group1 (Secure) and Group1 (NonSecure) 109 * (where the latter two are exposed as a single banked system register). 110 * In the state struct they are implemented as a 3-element array which 111 * can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants. 112 * If the CPU doesn't support EL3 then the G1 element is unused. 113 * 114 * These constants are also used to communicate the group to use for 115 * an interrupt or SGI when it is passed between the cpu interface and 116 * the redistributor or distributor. For those purposes the receiving end 117 * must be prepared to cope with a Group 1 Secure interrupt even if it does 118 * not have security support enabled, because security can be disabled 119 * independently in the CPU and in the GIC. In that case the receiver should 120 * treat an incoming Group 1 Secure interrupt as if it were Group 0. 121 * (This architectural requirement is why the _G1 element is the unused one 122 * in a no-EL3 CPU: we would otherwise have to translate back and forth 123 * between (G0, G1NS) from the distributor and (G0, G1) in the CPU i/f.) 124 */ 125 #define GICV3_G0 0 126 #define GICV3_G1 1 127 #define GICV3_G1NS 2 128 129 /* ICC_CTLR_EL1, GICD_STATUSR and GICR_STATUSR are banked but not 130 * group-related, so those indices are just 0 for S and 1 for NS. 131 * (If the CPU or the GIC, respectively, don't support the Security 132 * extensions then the S element is unused.) 133 */ 134 #define GICV3_S 0 135 #define GICV3_NS 1 136 137 typedef struct { 138 int irq; 139 uint8_t prio; 140 int grp; 141 } PendingIrq; 142 143 struct GICv3CPUState { 144 GICv3State *gic; 145 CPUState *cpu; 146 qemu_irq parent_irq; 147 qemu_irq parent_fiq; 148 149 /* Redistributor */ 150 uint32_t level; /* Current IRQ level */ 151 /* RD_base page registers */ 152 uint32_t gicr_ctlr; 153 uint64_t gicr_typer; 154 uint32_t gicr_statusr[2]; 155 uint32_t gicr_waker; 156 uint64_t gicr_propbaser; 157 uint64_t gicr_pendbaser; 158 /* SGI_base page registers */ 159 uint32_t gicr_igroupr0; 160 uint32_t gicr_ienabler0; 161 uint32_t gicr_ipendr0; 162 uint32_t gicr_iactiver0; 163 uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */ 164 uint32_t gicr_igrpmodr0; 165 uint32_t gicr_nsacr; 166 uint8_t gicr_ipriorityr[GIC_INTERNAL]; 167 168 /* CPU interface */ 169 uint64_t icc_ctlr_el1[2]; 170 uint64_t icc_pmr_el1; 171 uint64_t icc_bpr[3]; 172 uint64_t icc_apr[3][4]; 173 uint64_t icc_igrpen[3]; 174 uint64_t icc_ctlr_el3; 175 176 /* Current highest priority pending interrupt for this CPU. 177 * This is cached information that can be recalculated from the 178 * real state above; it doesn't need to be migrated. 179 */ 180 PendingIrq hppi; 181 /* This is temporary working state, to avoid a malloc in gicv3_update() */ 182 bool seenbetter; 183 }; 184 185 struct GICv3State { 186 /*< private >*/ 187 SysBusDevice parent_obj; 188 /*< public >*/ 189 190 MemoryRegion iomem_dist; /* Distributor */ 191 MemoryRegion iomem_redist; /* Redistributors */ 192 193 uint32_t num_cpu; 194 uint32_t num_irq; 195 uint32_t revision; 196 bool security_extn; 197 bool irq_reset_nonsecure; 198 199 int dev_fd; /* kvm device fd if backed by kvm vgic support */ 200 Error *migration_blocker; 201 202 /* Distributor */ 203 204 /* for a GIC with the security extensions the NS banked version of this 205 * register is just an alias of bit 1 of the S banked version. 206 */ 207 uint32_t gicd_ctlr; 208 uint32_t gicd_statusr[2]; 209 GIC_DECLARE_BITMAP(group); /* GICD_IGROUPR */ 210 GIC_DECLARE_BITMAP(grpmod); /* GICD_IGRPMODR */ 211 GIC_DECLARE_BITMAP(enabled); /* GICD_ISENABLER */ 212 GIC_DECLARE_BITMAP(pending); /* GICD_ISPENDR */ 213 GIC_DECLARE_BITMAP(active); /* GICD_ISACTIVER */ 214 GIC_DECLARE_BITMAP(level); /* Current level */ 215 GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */ 216 uint8_t gicd_ipriority[GICV3_MAXIRQ]; 217 uint64_t gicd_irouter[GICV3_MAXIRQ]; 218 /* Cached information: pointer to the cpu i/f for the CPUs specified 219 * in the IROUTER registers 220 */ 221 GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ]; 222 uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)]; 223 224 GICv3CPUState *cpu; 225 }; 226 227 #define GICV3_BITMAP_ACCESSORS(BMP) \ 228 static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq) \ 229 { \ 230 gic_bmp_set_bit(irq, s->BMP); \ 231 } \ 232 static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq) \ 233 { \ 234 return gic_bmp_test_bit(irq, s->BMP); \ 235 } \ 236 static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \ 237 { \ 238 gic_bmp_clear_bit(irq, s->BMP); \ 239 } \ 240 static inline void gicv3_gicd_##BMP##_replace(GICv3State *s, \ 241 int irq, int value) \ 242 { \ 243 gic_bmp_replace_bit(irq, s->BMP, value); \ 244 } 245 246 GICV3_BITMAP_ACCESSORS(group) 247 GICV3_BITMAP_ACCESSORS(grpmod) 248 GICV3_BITMAP_ACCESSORS(enabled) 249 GICV3_BITMAP_ACCESSORS(pending) 250 GICV3_BITMAP_ACCESSORS(active) 251 GICV3_BITMAP_ACCESSORS(level) 252 GICV3_BITMAP_ACCESSORS(edge_trigger) 253 254 #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common" 255 #define ARM_GICV3_COMMON(obj) \ 256 OBJECT_CHECK(GICv3State, (obj), TYPE_ARM_GICV3_COMMON) 257 #define ARM_GICV3_COMMON_CLASS(klass) \ 258 OBJECT_CLASS_CHECK(ARMGICv3CommonClass, (klass), TYPE_ARM_GICV3_COMMON) 259 #define ARM_GICV3_COMMON_GET_CLASS(obj) \ 260 OBJECT_GET_CLASS(ARMGICv3CommonClass, (obj), TYPE_ARM_GICV3_COMMON) 261 262 typedef struct ARMGICv3CommonClass { 263 /*< private >*/ 264 SysBusDeviceClass parent_class; 265 /*< public >*/ 266 267 void (*pre_save)(GICv3State *s); 268 void (*post_load)(GICv3State *s); 269 } ARMGICv3CommonClass; 270 271 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, 272 const MemoryRegionOps *ops); 273 274 #endif 275