1 /* 2 * ARM GIC support 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Copyright (c) 2015 Huawei. 6 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 7 * Written by Peter Maydell 8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifndef HW_ARM_GICV3_COMMON_H 25 #define HW_ARM_GICV3_COMMON_H 26 27 #include "hw/sysbus.h" 28 #include "hw/intc/arm_gic_common.h" 29 #include "qom/object.h" 30 31 /* 32 * Maximum number of possible interrupts, determined by the GIC architecture. 33 * Note that this does not include LPIs. When implemented, these should be 34 * dealt with separately. 35 */ 36 #define GICV3_MAXIRQ 1020 37 #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL) 38 39 #define GICV3_LPI_INTID_START 8192 40 41 /* 42 * The redistributor in GICv3 has two 64KB frames per CPU; in 43 * GICv4 it has four 64KB frames per CPU. 44 */ 45 #define GICV3_REDIST_SIZE 0x20000 46 #define GICV4_REDIST_SIZE 0x40000 47 48 /* Number of SGI target-list bits */ 49 #define GICV3_TARGETLIST_BITS 16 50 51 /* Maximum number of list registers (architectural limit) */ 52 #define GICV3_LR_MAX 16 53 54 /* Minimum BPR for Secure, or when security not enabled */ 55 #define GIC_MIN_BPR 0 56 /* Minimum BPR for Nonsecure when security is enabled */ 57 #define GIC_MIN_BPR_NS (GIC_MIN_BPR + 1) 58 59 /* For some distributor fields we want to model the array of 32-bit 60 * register values which hold various bitmaps corresponding to enabled, 61 * pending, etc bits. These macros and functions facilitate that; the 62 * APIs are generally modelled on the generic bitmap.h functions 63 * (which are unsuitable here because they use 'unsigned long' as the 64 * underlying storage type, which is very awkward when you need to 65 * access the data as 32-bit values.) 66 * Each bitmap contains a bit for each interrupt. Although there is 67 * space for the PPIs and SGIs, those bits (the first 32) are never 68 * used as that state lives in the redistributor. The unused bits are 69 * provided purely so that interrupt X's state is always in bit X; this 70 * avoids bugs where we forget to subtract GIC_INTERNAL from an 71 * interrupt number. 72 */ 73 #define GICV3_BMP_SIZE DIV_ROUND_UP(GICV3_MAXIRQ, 32) 74 75 #define GIC_DECLARE_BITMAP(name) \ 76 uint32_t name[GICV3_BMP_SIZE] 77 78 #define GIC_BIT_MASK(nr) (1U << ((nr) % 32)) 79 #define GIC_BIT_WORD(nr) ((nr) / 32) 80 81 static inline void gic_bmp_set_bit(int nr, uint32_t *addr) 82 { 83 uint32_t mask = GIC_BIT_MASK(nr); 84 uint32_t *p = addr + GIC_BIT_WORD(nr); 85 86 *p |= mask; 87 } 88 89 static inline void gic_bmp_clear_bit(int nr, uint32_t *addr) 90 { 91 uint32_t mask = GIC_BIT_MASK(nr); 92 uint32_t *p = addr + GIC_BIT_WORD(nr); 93 94 *p &= ~mask; 95 } 96 97 static inline int gic_bmp_test_bit(int nr, const uint32_t *addr) 98 { 99 return 1U & (addr[GIC_BIT_WORD(nr)] >> (nr & 31)); 100 } 101 102 static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val) 103 { 104 uint32_t mask = GIC_BIT_MASK(nr); 105 uint32_t *p = addr + GIC_BIT_WORD(nr); 106 107 *p &= ~mask; 108 *p |= (val & 1U) << (nr % 32); 109 } 110 111 /* Return a pointer to the 32-bit word containing the specified bit. */ 112 static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr) 113 { 114 return addr + GIC_BIT_WORD(nr); 115 } 116 117 typedef struct GICv3State GICv3State; 118 typedef struct GICv3CPUState GICv3CPUState; 119 120 /* Some CPU interface registers come in three flavours: 121 * Group0, Group1 (Secure) and Group1 (NonSecure) 122 * (where the latter two are exposed as a single banked system register). 123 * In the state struct they are implemented as a 3-element array which 124 * can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants. 125 * If the CPU doesn't support EL3 then the G1 element is unused. 126 * 127 * These constants are also used to communicate the group to use for 128 * an interrupt or SGI when it is passed between the cpu interface and 129 * the redistributor or distributor. For those purposes the receiving end 130 * must be prepared to cope with a Group 1 Secure interrupt even if it does 131 * not have security support enabled, because security can be disabled 132 * independently in the CPU and in the GIC. In that case the receiver should 133 * treat an incoming Group 1 Secure interrupt as if it were Group 0. 134 * (This architectural requirement is why the _G1 element is the unused one 135 * in a no-EL3 CPU: we would otherwise have to translate back and forth 136 * between (G0, G1NS) from the distributor and (G0, G1) in the CPU i/f.) 137 */ 138 #define GICV3_G0 0 139 #define GICV3_G1 1 140 #define GICV3_G1NS 2 141 142 /* ICC_CTLR_EL1, GICD_STATUSR and GICR_STATUSR are banked but not 143 * group-related, so those indices are just 0 for S and 1 for NS. 144 * (If the CPU or the GIC, respectively, don't support the Security 145 * extensions then the S element is unused.) 146 */ 147 #define GICV3_S 0 148 #define GICV3_NS 1 149 150 typedef struct { 151 int irq; 152 uint8_t prio; 153 int grp; 154 } PendingIrq; 155 156 struct GICv3CPUState { 157 GICv3State *gic; 158 CPUState *cpu; 159 qemu_irq parent_irq; 160 qemu_irq parent_fiq; 161 qemu_irq parent_virq; 162 qemu_irq parent_vfiq; 163 164 /* Redistributor */ 165 uint32_t level; /* Current IRQ level */ 166 /* RD_base page registers */ 167 uint32_t gicr_ctlr; 168 uint64_t gicr_typer; 169 uint32_t gicr_statusr[2]; 170 uint32_t gicr_waker; 171 uint64_t gicr_propbaser; 172 uint64_t gicr_pendbaser; 173 /* SGI_base page registers */ 174 uint32_t gicr_igroupr0; 175 uint32_t gicr_ienabler0; 176 uint32_t gicr_ipendr0; 177 uint32_t gicr_iactiver0; 178 uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */ 179 uint32_t gicr_igrpmodr0; 180 uint32_t gicr_nsacr; 181 uint8_t gicr_ipriorityr[GIC_INTERNAL]; 182 /* VLPI_base page registers */ 183 uint64_t gicr_vpropbaser; 184 uint64_t gicr_vpendbaser; 185 186 /* CPU interface */ 187 uint64_t icc_sre_el1; 188 uint64_t icc_ctlr_el1[2]; 189 uint64_t icc_pmr_el1; 190 uint64_t icc_bpr[3]; 191 uint64_t icc_apr[3][4]; 192 uint64_t icc_igrpen[3]; 193 uint64_t icc_ctlr_el3; 194 195 /* Virtualization control interface */ 196 uint64_t ich_apr[3][4]; /* ich_apr[GICV3_G1][x] never used */ 197 uint64_t ich_hcr_el2; 198 uint64_t ich_lr_el2[GICV3_LR_MAX]; 199 uint64_t ich_vmcr_el2; 200 201 /* Properties of the CPU interface. These are initialized from 202 * the settings in the CPU proper. 203 * If the number of implemented list registers is 0 then the 204 * virtualization support is not implemented. 205 */ 206 int num_list_regs; 207 int vpribits; /* number of virtual priority bits */ 208 int vprebits; /* number of virtual preemption bits */ 209 210 /* Current highest priority pending interrupt for this CPU. 211 * This is cached information that can be recalculated from the 212 * real state above; it doesn't need to be migrated. 213 */ 214 PendingIrq hppi; 215 216 /* 217 * Cached information recalculated from LPI tables 218 * in guest memory 219 */ 220 PendingIrq hpplpi; 221 222 /* Cached information recalculated from vLPI tables in guest memory */ 223 PendingIrq hppvlpi; 224 225 /* This is temporary working state, to avoid a malloc in gicv3_update() */ 226 bool seenbetter; 227 }; 228 229 /* 230 * The redistributor pages might be split into more than one region 231 * on some machine types if there are many CPUs. 232 */ 233 typedef struct GICv3RedistRegion { 234 GICv3State *gic; 235 MemoryRegion iomem; 236 uint32_t cpuidx; /* index of first CPU this region covers */ 237 } GICv3RedistRegion; 238 239 struct GICv3State { 240 /*< private >*/ 241 SysBusDevice parent_obj; 242 /*< public >*/ 243 244 MemoryRegion iomem_dist; /* Distributor */ 245 GICv3RedistRegion *redist_regions; /* Redistributor Regions */ 246 uint32_t *redist_region_count; /* redistributor count within each region */ 247 uint32_t nb_redist_regions; /* number of redist regions */ 248 249 uint32_t num_cpu; 250 uint32_t num_irq; 251 uint32_t revision; 252 bool lpi_enable; 253 bool security_extn; 254 bool irq_reset_nonsecure; 255 bool gicd_no_migration_shift_bug; 256 257 int dev_fd; /* kvm device fd if backed by kvm vgic support */ 258 Error *migration_blocker; 259 260 MemoryRegion *dma; 261 AddressSpace dma_as; 262 263 /* Distributor */ 264 265 /* for a GIC with the security extensions the NS banked version of this 266 * register is just an alias of bit 1 of the S banked version. 267 */ 268 uint32_t gicd_ctlr; 269 uint32_t gicd_statusr[2]; 270 GIC_DECLARE_BITMAP(group); /* GICD_IGROUPR */ 271 GIC_DECLARE_BITMAP(grpmod); /* GICD_IGRPMODR */ 272 GIC_DECLARE_BITMAP(enabled); /* GICD_ISENABLER */ 273 GIC_DECLARE_BITMAP(pending); /* GICD_ISPENDR */ 274 GIC_DECLARE_BITMAP(active); /* GICD_ISACTIVER */ 275 GIC_DECLARE_BITMAP(level); /* Current level */ 276 GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */ 277 uint8_t gicd_ipriority[GICV3_MAXIRQ]; 278 uint64_t gicd_irouter[GICV3_MAXIRQ]; 279 /* Cached information: pointer to the cpu i/f for the CPUs specified 280 * in the IROUTER registers 281 */ 282 GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ]; 283 uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)]; 284 285 GICv3CPUState *cpu; 286 /* List of all ITSes connected to this GIC */ 287 GPtrArray *itslist; 288 }; 289 290 #define GICV3_BITMAP_ACCESSORS(BMP) \ 291 static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq) \ 292 { \ 293 gic_bmp_set_bit(irq, s->BMP); \ 294 } \ 295 static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq) \ 296 { \ 297 return gic_bmp_test_bit(irq, s->BMP); \ 298 } \ 299 static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \ 300 { \ 301 gic_bmp_clear_bit(irq, s->BMP); \ 302 } \ 303 static inline void gicv3_gicd_##BMP##_replace(GICv3State *s, \ 304 int irq, int value) \ 305 { \ 306 gic_bmp_replace_bit(irq, s->BMP, value); \ 307 } 308 309 GICV3_BITMAP_ACCESSORS(group) 310 GICV3_BITMAP_ACCESSORS(grpmod) 311 GICV3_BITMAP_ACCESSORS(enabled) 312 GICV3_BITMAP_ACCESSORS(pending) 313 GICV3_BITMAP_ACCESSORS(active) 314 GICV3_BITMAP_ACCESSORS(level) 315 GICV3_BITMAP_ACCESSORS(edge_trigger) 316 317 #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common" 318 typedef struct ARMGICv3CommonClass ARMGICv3CommonClass; 319 DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass, 320 ARM_GICV3_COMMON, TYPE_ARM_GICV3_COMMON) 321 322 struct ARMGICv3CommonClass { 323 /*< private >*/ 324 SysBusDeviceClass parent_class; 325 /*< public >*/ 326 327 void (*pre_save)(GICv3State *s); 328 void (*post_load)(GICv3State *s); 329 }; 330 331 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, 332 const MemoryRegionOps *ops); 333 334 #endif 335