1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * LoongArch 7A1000 I/O interrupt controller definitions 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "hw/sysbus.h" 9 10 #define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi" 11 OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI) 12 13 /* MSI irq start from 32 to 255 */ 14 #define PCH_MSI_IRQ_START 32 15 #define PCH_MSI_IRQ_END 255 16 #define PCH_MSI_IRQ_NUM 224 17 18 struct LoongArchPCHMSI { 19 SysBusDevice parent_obj; 20 qemu_irq *pch_msi_irq; 21 MemoryRegion msi_mmio; 22 /* irq base passed to upper extioi intc */ 23 unsigned int irq_base; 24 unsigned int irq_num; 25 }; 26