1*e8bd336dSYongbok Kim /* 2*e8bd336dSYongbok Kim * This file is subject to the terms and conditions of the GNU General Public 3*e8bd336dSYongbok Kim * License. See the file "COPYING" in the main directory of this archive 4*e8bd336dSYongbok Kim * for more details. 5*e8bd336dSYongbok Kim * 6*e8bd336dSYongbok Kim * Copyright (C) 2000, 07 MIPS Technologies, Inc. 7*e8bd336dSYongbok Kim * Copyright (C) 2016 Imagination Technologies 8*e8bd336dSYongbok Kim * 9*e8bd336dSYongbok Kim */ 10*e8bd336dSYongbok Kim 11*e8bd336dSYongbok Kim #ifndef _MIPS_GIC_H 12*e8bd336dSYongbok Kim #define _MIPS_GIC_H 13*e8bd336dSYongbok Kim 14*e8bd336dSYongbok Kim #include "hw/timer/mips_gictimer.h" 15*e8bd336dSYongbok Kim #include "cpu.h" 16*e8bd336dSYongbok Kim /* 17*e8bd336dSYongbok Kim * GIC Specific definitions 18*e8bd336dSYongbok Kim */ 19*e8bd336dSYongbok Kim 20*e8bd336dSYongbok Kim /* The MIPS default location */ 21*e8bd336dSYongbok Kim #define GIC_BASE_ADDR 0x1bdc0000ULL 22*e8bd336dSYongbok Kim #define GIC_ADDRSPACE_SZ (128 * 1024) 23*e8bd336dSYongbok Kim 24*e8bd336dSYongbok Kim /* Constants */ 25*e8bd336dSYongbok Kim #define GIC_POL_POS 1 26*e8bd336dSYongbok Kim #define GIC_POL_NEG 0 27*e8bd336dSYongbok Kim #define GIC_TRIG_EDGE 1 28*e8bd336dSYongbok Kim #define GIC_TRIG_LEVEL 0 29*e8bd336dSYongbok Kim 30*e8bd336dSYongbok Kim #define MSK(n) ((1ULL << (n)) - 1) 31*e8bd336dSYongbok Kim 32*e8bd336dSYongbok Kim /* GIC Address Space */ 33*e8bd336dSYongbok Kim #define SHARED_SECTION_OFS 0x0000 34*e8bd336dSYongbok Kim #define SHARED_SECTION_SIZE 0x8000 35*e8bd336dSYongbok Kim #define VP_LOCAL_SECTION_OFS 0x8000 36*e8bd336dSYongbok Kim #define VP_LOCAL_SECTION_SIZE 0x4000 37*e8bd336dSYongbok Kim #define VP_OTHER_SECTION_OFS 0xc000 38*e8bd336dSYongbok Kim #define VP_OTHER_SECTION_SIZE 0x4000 39*e8bd336dSYongbok Kim #define USM_VISIBLE_SECTION_OFS 0x10000 40*e8bd336dSYongbok Kim #define USM_VISIBLE_SECTION_SIZE 0x10000 41*e8bd336dSYongbok Kim 42*e8bd336dSYongbok Kim /* Register Map for Shared Section */ 43*e8bd336dSYongbok Kim 44*e8bd336dSYongbok Kim #define GIC_SH_CONFIG_OFS 0x0000 45*e8bd336dSYongbok Kim 46*e8bd336dSYongbok Kim /* Shared Global Counter */ 47*e8bd336dSYongbok Kim #define GIC_SH_COUNTERLO_OFS 0x0010 48*e8bd336dSYongbok Kim #define GIC_SH_COUNTERHI_OFS 0x0014 49*e8bd336dSYongbok Kim #define GIC_SH_REVISIONID_OFS 0x0020 50*e8bd336dSYongbok Kim 51*e8bd336dSYongbok Kim /* Set/Clear corresponding bit in Edge Detect Register */ 52*e8bd336dSYongbok Kim #define GIC_SH_WEDGE_OFS 0x0280 53*e8bd336dSYongbok Kim 54*e8bd336dSYongbok Kim /* Reset Mask - Disables Interrupt */ 55*e8bd336dSYongbok Kim #define GIC_SH_RMASK_OFS 0x0300 56*e8bd336dSYongbok Kim #define GIC_SH_RMASK_LAST_OFS 0x031c 57*e8bd336dSYongbok Kim 58*e8bd336dSYongbok Kim /* Set Mask (WO) - Enables Interrupt */ 59*e8bd336dSYongbok Kim #define GIC_SH_SMASK_OFS 0x0380 60*e8bd336dSYongbok Kim #define GIC_SH_SMASK_LAST_OFS 0x039c 61*e8bd336dSYongbok Kim 62*e8bd336dSYongbok Kim /* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ 63*e8bd336dSYongbok Kim #define GIC_SH_MASK_OFS 0x0400 64*e8bd336dSYongbok Kim #define GIC_SH_MASK_LAST_OFS 0x041c 65*e8bd336dSYongbok Kim 66*e8bd336dSYongbok Kim /* Pending Global Interrupts (RO) */ 67*e8bd336dSYongbok Kim #define GIC_SH_PEND_OFS 0x0480 68*e8bd336dSYongbok Kim #define GIC_SH_PEND_LAST_OFS 0x049c 69*e8bd336dSYongbok Kim 70*e8bd336dSYongbok Kim #define GIC_SH_MAP0_PIN_OFS 0x0500 71*e8bd336dSYongbok Kim #define GIC_SH_MAP255_PIN_OFS 0x08fc 72*e8bd336dSYongbok Kim 73*e8bd336dSYongbok Kim #define GIC_SH_MAP0_VP_OFS 0x2000 74*e8bd336dSYongbok Kim #define GIC_SH_MAP255_VP_LAST_OFS 0x3fe4 75*e8bd336dSYongbok Kim 76*e8bd336dSYongbok Kim /* Register Map for Local Section */ 77*e8bd336dSYongbok Kim #define GIC_VP_CTL_OFS 0x0000 78*e8bd336dSYongbok Kim #define GIC_VP_PEND_OFS 0x0004 79*e8bd336dSYongbok Kim #define GIC_VP_MASK_OFS 0x0008 80*e8bd336dSYongbok Kim #define GIC_VP_RMASK_OFS 0x000c 81*e8bd336dSYongbok Kim #define GIC_VP_SMASK_OFS 0x0010 82*e8bd336dSYongbok Kim #define GIC_VP_WD_MAP_OFS 0x0040 83*e8bd336dSYongbok Kim #define GIC_VP_COMPARE_MAP_OFS 0x0044 84*e8bd336dSYongbok Kim #define GIC_VP_TIMER_MAP_OFS 0x0048 85*e8bd336dSYongbok Kim #define GIC_VP_FDC_MAP_OFS 0x004c 86*e8bd336dSYongbok Kim #define GIC_VP_PERFCTR_MAP_OFS 0x0050 87*e8bd336dSYongbok Kim #define GIC_VP_SWINT0_MAP_OFS 0x0054 88*e8bd336dSYongbok Kim #define GIC_VP_SWINT1_MAP_OFS 0x0058 89*e8bd336dSYongbok Kim #define GIC_VP_OTHER_ADDR_OFS 0x0080 90*e8bd336dSYongbok Kim #define GIC_VP_IDENT_OFS 0x0088 91*e8bd336dSYongbok Kim #define GIC_VP_WD_CONFIG0_OFS 0x0090 92*e8bd336dSYongbok Kim #define GIC_VP_WD_COUNT0_OFS 0x0094 93*e8bd336dSYongbok Kim #define GIC_VP_WD_INITIAL0_OFS 0x0098 94*e8bd336dSYongbok Kim #define GIC_VP_COMPARE_LO_OFS 0x00a0 95*e8bd336dSYongbok Kim #define GIC_VP_COMPARE_HI_OFS 0x00a4 96*e8bd336dSYongbok Kim #define GIC_VL_BRK_GROUP 0x3080 97*e8bd336dSYongbok Kim 98*e8bd336dSYongbok Kim /* User-Mode Visible Section Register */ 99*e8bd336dSYongbok Kim /* Read-only alias for GIC Shared CounterLo */ 100*e8bd336dSYongbok Kim #define GIC_USER_MODE_COUNTERLO 0x0000 101*e8bd336dSYongbok Kim /* Read-only alias for GIC Shared CounterHi */ 102*e8bd336dSYongbok Kim #define GIC_USER_MODE_COUNTERHI 0x0004 103*e8bd336dSYongbok Kim 104*e8bd336dSYongbok Kim /* Masks */ 105*e8bd336dSYongbok Kim #define GIC_SH_CONFIG_COUNTSTOP_SHF 28 106*e8bd336dSYongbok Kim #define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) 107*e8bd336dSYongbok Kim #define GIC_SH_CONFIG_COUNTBITS_SHF 24 108*e8bd336dSYongbok Kim #define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF) 109*e8bd336dSYongbok Kim #define GIC_SH_CONFIG_NUMINTRS_SHF 16 110*e8bd336dSYongbok Kim #define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF) 111*e8bd336dSYongbok Kim #define GIC_SH_CONFIG_PVPS_SHF 0 112*e8bd336dSYongbok Kim #define GIC_SH_CONFIG_PVPS_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPS_SHF) 113*e8bd336dSYongbok Kim 114*e8bd336dSYongbok Kim #define GIC_SH_WEDGE_RW_SHF 31 115*e8bd336dSYongbok Kim #define GIC_SH_WEDGE_RW_MSK (MSK(1) << GIC_SH_WEDGE_RW_SHF) 116*e8bd336dSYongbok Kim 117*e8bd336dSYongbok Kim #define GIC_MAP_TO_PIN_SHF 31 118*e8bd336dSYongbok Kim #define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF) 119*e8bd336dSYongbok Kim #define GIC_MAP_TO_NMI_SHF 30 120*e8bd336dSYongbok Kim #define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF) 121*e8bd336dSYongbok Kim #define GIC_MAP_TO_YQ_SHF 29 122*e8bd336dSYongbok Kim #define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF) 123*e8bd336dSYongbok Kim #define GIC_MAP_SHF 0 124*e8bd336dSYongbok Kim #define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF) 125*e8bd336dSYongbok Kim #define GIC_MAP_TO_PIN_REG_MSK \ 126*e8bd336dSYongbok Kim (GIC_MAP_TO_PIN_MSK | GIC_MAP_TO_NMI_MSK | GIC_MAP_TO_YQ_MSK | GIC_MAP_MSK) 127*e8bd336dSYongbok Kim 128*e8bd336dSYongbok Kim /* GIC_VP_CTL Masks */ 129*e8bd336dSYongbok Kim #define GIC_VP_CTL_FDC_RTBL_SHF 4 130*e8bd336dSYongbok Kim #define GIC_VP_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VP_CTL_FDC_RTBL_SHF) 131*e8bd336dSYongbok Kim #define GIC_VP_CTL_SWINT_RTBL_SHF 3 132*e8bd336dSYongbok Kim #define GIC_VP_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VP_CTL_SWINT_RTBL_SHF) 133*e8bd336dSYongbok Kim #define GIC_VP_CTL_PERFCNT_RTBL_SHF 2 134*e8bd336dSYongbok Kim #define GIC_VP_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VP_CTL_PERFCNT_RTBL_SHF) 135*e8bd336dSYongbok Kim #define GIC_VP_CTL_TIMER_RTBL_SHF 1 136*e8bd336dSYongbok Kim #define GIC_VP_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VP_CTL_TIMER_RTBL_SHF) 137*e8bd336dSYongbok Kim #define GIC_VP_CTL_EIC_MODE_SHF 0 138*e8bd336dSYongbok Kim #define GIC_VP_CTL_EIC_MODE_MSK (MSK(1) << GIC_VP_CTL_EIC_MODE_SHF) 139*e8bd336dSYongbok Kim 140*e8bd336dSYongbok Kim /* GIC_VP_MASK Masks */ 141*e8bd336dSYongbok Kim #define GIC_VP_MASK_FDC_SHF 6 142*e8bd336dSYongbok Kim #define GIC_VP_MASK_FDC_MSK (MSK(1) << GIC_VP_MASK_FDC_SHF) 143*e8bd336dSYongbok Kim #define GIC_VP_MASK_SWINT1_SHF 5 144*e8bd336dSYongbok Kim #define GIC_VP_MASK_SWINT1_MSK (MSK(1) << GIC_VP_MASK_SWINT1_SHF) 145*e8bd336dSYongbok Kim #define GIC_VP_MASK_SWINT0_SHF 4 146*e8bd336dSYongbok Kim #define GIC_VP_MASK_SWINT0_MSK (MSK(1) << GIC_VP_MASK_SWINT0_SHF) 147*e8bd336dSYongbok Kim #define GIC_VP_MASK_PERFCNT_SHF 3 148*e8bd336dSYongbok Kim #define GIC_VP_MASK_PERFCNT_MSK (MSK(1) << GIC_VP_MASK_PERFCNT_SHF) 149*e8bd336dSYongbok Kim #define GIC_VP_MASK_TIMER_SHF 2 150*e8bd336dSYongbok Kim #define GIC_VP_MASK_TIMER_MSK (MSK(1) << GIC_VP_MASK_TIMER_SHF) 151*e8bd336dSYongbok Kim #define GIC_VP_MASK_CMP_SHF 1 152*e8bd336dSYongbok Kim #define GIC_VP_MASK_CMP_MSK (MSK(1) << GIC_VP_MASK_CMP_SHF) 153*e8bd336dSYongbok Kim #define GIC_VP_MASK_WD_SHF 0 154*e8bd336dSYongbok Kim #define GIC_VP_MASK_WD_MSK (MSK(1) << GIC_VP_MASK_WD_SHF) 155*e8bd336dSYongbok Kim #define GIC_VP_SET_RESET_MSK (MSK(7) << GIC_VP_MASK_WD_SHF) 156*e8bd336dSYongbok Kim 157*e8bd336dSYongbok Kim #define GIC_CPU_INT_MAX 5 /* Core Interrupt 7 */ 158*e8bd336dSYongbok Kim #define GIC_CPU_PIN_OFFSET 2 159*e8bd336dSYongbok Kim 160*e8bd336dSYongbok Kim /* Local GIC interrupts. */ 161*e8bd336dSYongbok Kim #define GIC_NUM_LOCAL_INTRS 7 162*e8bd336dSYongbok Kim #define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */ 163*e8bd336dSYongbok Kim #define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */ 164*e8bd336dSYongbok Kim #define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */ 165*e8bd336dSYongbok Kim #define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */ 166*e8bd336dSYongbok Kim #define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */ 167*e8bd336dSYongbok Kim #define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */ 168*e8bd336dSYongbok Kim #define GIC_LOCAL_INT_WD 0 /* GIC watchdog */ 169*e8bd336dSYongbok Kim 170*e8bd336dSYongbok Kim #define TYPE_MIPS_GIC "mips-gic" 171*e8bd336dSYongbok Kim #define MIPS_GIC(obj) OBJECT_CHECK(MIPSGICState, (obj), TYPE_MIPS_GIC) 172*e8bd336dSYongbok Kim 173*e8bd336dSYongbok Kim /* Support up to 32 VPs and 256 IRQs */ 174*e8bd336dSYongbok Kim #define GIC_MAX_VPS 32 175*e8bd336dSYongbok Kim #define GIC_MAX_INTRS 256 176*e8bd336dSYongbok Kim 177*e8bd336dSYongbok Kim typedef struct MIPSGICState MIPSGICState; 178*e8bd336dSYongbok Kim typedef struct MIPSGICIRQState MIPSGICIRQState; 179*e8bd336dSYongbok Kim typedef struct MIPSGICVPState MIPSGICVPState; 180*e8bd336dSYongbok Kim 181*e8bd336dSYongbok Kim struct MIPSGICIRQState { 182*e8bd336dSYongbok Kim uint8_t enabled; 183*e8bd336dSYongbok Kim uint8_t pending; 184*e8bd336dSYongbok Kim uint32_t map_pin; 185*e8bd336dSYongbok Kim int32_t map_vp; 186*e8bd336dSYongbok Kim qemu_irq irq; 187*e8bd336dSYongbok Kim }; 188*e8bd336dSYongbok Kim 189*e8bd336dSYongbok Kim struct MIPSGICVPState { 190*e8bd336dSYongbok Kim uint32_t ctl; 191*e8bd336dSYongbok Kim uint32_t pend; 192*e8bd336dSYongbok Kim uint32_t mask; 193*e8bd336dSYongbok Kim uint32_t compare_map; 194*e8bd336dSYongbok Kim uint32_t other_addr; 195*e8bd336dSYongbok Kim CPUMIPSState *env; 196*e8bd336dSYongbok Kim }; 197*e8bd336dSYongbok Kim 198*e8bd336dSYongbok Kim struct MIPSGICState { 199*e8bd336dSYongbok Kim SysBusDevice parent_obj; 200*e8bd336dSYongbok Kim MemoryRegion mr; 201*e8bd336dSYongbok Kim 202*e8bd336dSYongbok Kim /* Shared Section Registers */ 203*e8bd336dSYongbok Kim uint32_t sh_config; 204*e8bd336dSYongbok Kim MIPSGICIRQState *irq_state; 205*e8bd336dSYongbok Kim 206*e8bd336dSYongbok Kim /* VP Local/Other Section Registers */ 207*e8bd336dSYongbok Kim MIPSGICVPState *vps; 208*e8bd336dSYongbok Kim 209*e8bd336dSYongbok Kim /* GIC VP Timer */ 210*e8bd336dSYongbok Kim MIPSGICTimerState *gic_timer; 211*e8bd336dSYongbok Kim 212*e8bd336dSYongbok Kim int32_t num_vps; 213*e8bd336dSYongbok Kim int32_t num_irq; 214*e8bd336dSYongbok Kim }; 215*e8bd336dSYongbok Kim 216*e8bd336dSYongbok Kim #endif /* _MIPS_GIC_H */ 217