1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 #ifndef ASPEED_SCU_H 12 #define ASPEED_SCU_H 13 14 #include "hw/sysbus.h" 15 #include "qom/object.h" 16 17 #define TYPE_ASPEED_SCU "aspeed.scu" 18 OBJECT_DECLARE_TYPE(AspeedSCUState, AspeedSCUClass, ASPEED_SCU) 19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400" 20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500" 21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600" 22 23 #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) 24 #define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2) 25 26 struct AspeedSCUState { 27 /*< private >*/ 28 SysBusDevice parent_obj; 29 30 /*< public >*/ 31 MemoryRegion iomem; 32 33 uint32_t regs[ASPEED_AST2600_SCU_NR_REGS]; 34 uint32_t silicon_rev; 35 uint32_t hw_strap1; 36 uint32_t hw_strap2; 37 uint32_t hw_prot_key; 38 }; 39 40 #define AST2400_A0_SILICON_REV 0x02000303U 41 #define AST2400_A1_SILICON_REV 0x02010303U 42 #define AST2500_A0_SILICON_REV 0x04000303U 43 #define AST2500_A1_SILICON_REV 0x04010303U 44 #define AST2600_A0_SILICON_REV 0x05000303U 45 #define AST2600_A1_SILICON_REV 0x05010303U 46 #define AST2600_A2_SILICON_REV 0x05020303U 47 #define AST2600_A3_SILICON_REV 0x05030303U 48 49 #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) 50 51 extern bool is_supported_silicon_rev(uint32_t silicon_rev); 52 53 54 struct AspeedSCUClass { 55 SysBusDeviceClass parent_class; 56 57 const uint32_t *resets; 58 uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg); 59 uint32_t apb_divider; 60 uint32_t nr_regs; 61 const MemoryRegionOps *ops; 62 }; 63 64 #define ASPEED_SCU_PROT_KEY 0x1688A8A8 65 66 uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s); 67 68 /* 69 * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions 70 * were added. 71 * 72 * Original header file : 73 * arch/arm/mach-aspeed/include/mach/regs-scu.h 74 * 75 * Copyright (C) 2012-2020 ASPEED Technology Inc. 76 * 77 * This program is free software; you can redistribute it and/or modify 78 * it under the terms of the GNU General Public License version 2 as 79 * published by the Free Software Foundation. 80 * 81 * History : 82 * 1. 2012/12/29 Ryan Chen Create 83 */ 84 85 /* SCU08 Clock Selection Register 86 * 87 * 31 Enable Video Engine clock dynamic slow down 88 * 30:28 Video Engine clock slow down setting 89 * 27 2D Engine GCLK clock source selection 90 * 26 2D Engine GCLK clock throttling enable 91 * 25:23 APB PCLK divider selection 92 * 22:20 LPC Host LHCLK divider selection 93 * 19 LPC Host LHCLK clock generation/output enable control 94 * 18:16 MAC AHB bus clock divider selection 95 * 15 SD/SDIO clock running enable 96 * 14:12 SD/SDIO divider selection 97 * 11 Reserved 98 * 10:8 Video port output clock delay control bit 99 * 7 ARM CPU/AHB clock slow down enable 100 * 6:4 ARM CPU/AHB clock slow down setting 101 * 3:2 ECLK clock source selection 102 * 1 CPU/AHB clock slow down idle timer 103 * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4]) 104 */ 105 #define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7) 106 107 /* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC) 108 * 109 * 18 H-PLL parameter selection 110 * 0: Select H-PLL by strapping resistors 111 * 1: Select H-PLL by the programmed registers (SCU24[17:0]) 112 * 17 Enable H-PLL bypass mode 113 * 16 Turn off H-PLL 114 * 10:5 H-PLL Numerator 115 * 4 H-PLL Output Divider 116 * 3:0 H-PLL Denumerator 117 * 118 * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)] 119 */ 120 121 #define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18) 122 #define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17) 123 #define SCU_AST2400_H_PLL_OFF (0x1 << 16) 124 125 /* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC) 126 * 127 * 21 Enable H-PLL reset 128 * 20 Enable H-PLL bypass mode 129 * 19 Turn off H-PLL 130 * 18:13 H-PLL Post Divider 131 * 12:5 H-PLL Numerator (M) 132 * 4:0 H-PLL Denumerator (N) 133 * 134 * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1) 135 * 136 * The default frequency is 792Mhz when CLKIN = 24MHz 137 */ 138 139 #define SCU_H_PLL_BYPASS_EN (0x1 << 20) 140 #define SCU_H_PLL_OFF (0x1 << 19) 141 142 /* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC) 143 * 144 * 31:29 Software defined strapping registers 145 * 28:27 DRAM size setting (for VGA driver use) 146 * 26:24 DRAM configuration setting 147 * 23 Enable 25 MHz reference clock input 148 * 22 Enable GPIOE pass-through mode 149 * 21 Enable GPIOD pass-through mode 150 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 151 * 19 Disable ACPI function 152 * 23,18 Clock source selection 153 * 17 Enable BMC 2nd boot watchdog timer 154 * 16 SuperIO configuration address selection 155 * 15 VGA Class Code selection 156 * 14 Enable LPC dedicated reset pin function 157 * 13:12 SPI mode selection 158 * 11:10 CPU/AHB clock frequency ratio selection 159 * 9:8 H-PLL default clock frequency selection 160 * 7 Define MAC#2 interface 161 * 6 Define MAC#1 interface 162 * 5 Enable VGA BIOS ROM 163 * 4 Boot flash memory extended option 164 * 3:2 VGA memory size selection 165 * 1:0 BMC CPU boot code selection 166 */ 167 #define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29) 168 #define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) 169 170 #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27) 171 #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) 172 #define DRAM_SIZE_64MB 0 173 #define DRAM_SIZE_128MB 1 174 #define DRAM_SIZE_256MB 2 175 #define DRAM_SIZE_512MB 3 176 177 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24) 178 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) 179 180 #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) 181 #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) 182 #define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) 183 #define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19) 184 185 /* bit 23, 18 [1,0] */ 186 #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \ 187 | (((x) & 0x1) << 18)) 188 #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \ 189 | (((x) >> 18) & 0x1)) 190 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) 191 #define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23) 192 #define AST2400_CLK_24M_IN 0 193 #define AST2400_CLK_48M_IN 1 194 #define AST2400_CLK_25M_IN_24M_USB_CKI 2 195 #define AST2400_CLK_25M_IN_48M_USB_CKI 3 196 197 #define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18) 198 #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) 199 #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) 200 #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) 201 #define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) 202 203 #define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12) 204 #define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) 205 #define SCU_HW_STRAP_SPI_DIS 0 206 #define SCU_HW_STRAP_SPI_MASTER 1 207 #define SCU_HW_STRAP_SPI_M_S_EN 2 208 #define SCU_HW_STRAP_SPI_PASS_THROUGH 3 209 210 #define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10) 211 #define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3) 212 #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) 213 #define AST2400_CPU_AHB_RATIO_1_1 0 214 #define AST2400_CPU_AHB_RATIO_2_1 1 215 #define AST2400_CPU_AHB_RATIO_4_1 2 216 #define AST2400_CPU_AHB_RATIO_3_1 3 217 218 #define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3) 219 #define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) 220 #define AST2400_CPU_384MHZ 0 221 #define AST2400_CPU_360MHZ 1 222 #define AST2400_CPU_336MHZ 2 223 #define AST2400_CPU_408MHZ 3 224 225 #define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) 226 #define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) 227 #define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) 228 #define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) 229 230 #define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3) 231 #define SCU_HW_STRAP_VGA_MASK (0x3 << 2) 232 #define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2) 233 #define VGA_8M_DRAM 0 234 #define VGA_16M_DRAM 1 235 #define VGA_32M_DRAM 2 236 #define VGA_64M_DRAM 3 237 238 #define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x) 239 #define AST2400_NOR_BOOT 0 240 #define AST2400_NAND_BOOT 1 241 #define AST2400_SPI_BOOT 2 242 #define AST2400_DIS_BOOT 3 243 244 /* 245 * SCU70 Hardware strapping register definition (for Aspeed AST2500 246 * SoC and higher) 247 * 248 * 31 Enable SPI Flash Strap Auto Fetch Mode 249 * 30 Enable GPIO Strap Mode 250 * 29 Select UART Debug Port 251 * 28 Reserved (1) 252 * 27 Enable fast reset mode for ARM ICE debugger 253 * 26 Enable eSPI flash mode 254 * 25 Enable eSPI mode 255 * 24 Select DDR4 SDRAM 256 * 23 Select 25 MHz reference clock input mode 257 * 22 Enable GPIOE pass-through mode 258 * 21 Enable GPIOD pass-through mode 259 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 260 * 19 Enable ACPI function 261 * 18 Select USBCKI input frequency 262 * 17 Enable BMC 2nd boot watchdog timer 263 * 16 SuperIO configuration address selection 264 * 15 VGA Class Code selection 265 * 14 Select dedicated LPC reset input 266 * 13:12 SPI mode selection 267 * 11:9 AXI/AHB clock frequency ratio selection 268 * 8 Reserved (0) 269 * 7 Define MAC#2 interface 270 * 6 Define MAC#1 interface 271 * 5 Enable dedicated VGA BIOS ROM 272 * 4 Reserved (0) 273 * 3:2 VGA memory size selection 274 * 1 Reserved (1) 275 * 0 Disable CPU boot 276 */ 277 #define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31) 278 #define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30) 279 #define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29) 280 #define UART_DEBUG_UART1 0 281 #define UART_DEBUG_UART5 1 282 #define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28) 283 284 #define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27) 285 #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26) 286 #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25) 287 #define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24) 288 #define SCU_AST2500_HW_STRAP_25HZ_CLOCK_MODE (0x1 << 23) 289 290 #define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19) 291 #define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18) 292 #define USBCKI_FREQ_24MHZ 0 293 #define USBCKI_FREQ_28MHZ 1 294 295 #define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9) 296 #define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7) 297 #define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9) 298 #define AXI_AHB_RATIO_UNDEFINED 0 299 #define AXI_AHB_RATIO_2_1 1 300 #define AXI_AHB_RATIO_3_1 2 301 #define AXI_AHB_RATIO_4_1 3 302 #define AXI_AHB_RATIO_5_1 4 303 #define AXI_AHB_RATIO_6_1 5 304 #define AXI_AHB_RATIO_7_1 6 305 #define AXI_AHB_RATIO_8_1 7 306 307 #define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1) 308 #define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0) 309 310 #define AST2500_HW_STRAP1_DEFAULTS ( \ 311 SCU_AST2500_HW_STRAP_RESERVED28 | \ 312 SCU_HW_STRAP_2ND_BOOT_WDT | \ 313 SCU_HW_STRAP_VGA_CLASS_CODE | \ 314 SCU_HW_STRAP_LPC_RESET_PIN | \ 315 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 316 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 317 SCU_AST2500_HW_STRAP_RESERVED1) 318 319 #endif /* ASPEED_SCU_H */ 320