1 /* 2 * ASPEED SDRAM Memory Controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 #ifndef ASPEED_SDMC_H 10 #define ASPEED_SDMC_H 11 12 #include "hw/sysbus.h" 13 #include "qom/object.h" 14 15 #define TYPE_ASPEED_SDMC "aspeed.sdmc" 16 typedef struct AspeedSDMCClass AspeedSDMCClass; 17 typedef struct AspeedSDMCState AspeedSDMCState; 18 DECLARE_OBJ_CHECKERS(AspeedSDMCState, AspeedSDMCClass, 19 ASPEED_SDMC, TYPE_ASPEED_SDMC) 20 #define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400" 21 #define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500" 22 #define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600" 23 24 /* 25 * SDMC has 174 documented registers. In addition the u-boot device tree 26 * describes the following regions: 27 * - PHY status regs at offset 0x400, length 0x200 28 * - PHY setting regs at offset 0x100, length 0x300 29 * 30 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 31 * system: one is in the SDRAM MC (memory controller) which is used in run 32 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 33 * training. 34 */ 35 #define ASPEED_SDMC_NR_REGS (0x500 >> 2) 36 37 struct AspeedSDMCState { 38 /*< private >*/ 39 SysBusDevice parent_obj; 40 41 /*< public >*/ 42 MemoryRegion iomem; 43 44 uint32_t regs[ASPEED_SDMC_NR_REGS]; 45 uint64_t ram_size; 46 uint64_t max_ram_size; 47 }; 48 49 50 struct AspeedSDMCClass { 51 SysBusDeviceClass parent_class; 52 53 uint64_t max_ram_size; 54 const uint64_t *valid_ram_sizes; 55 uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data); 56 void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data); 57 }; 58 59 #endif /* ASPEED_SDMC_H */ 60