1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2015 Imagination Technologies 7 * 8 */ 9 10 #ifndef MIPS_CMGCR_H 11 #define MIPS_CMGCR_H 12 13 #include "hw/sysbus.h" 14 #include "qom/object.h" 15 16 #define TYPE_MIPS_GCR "mips-gcr" 17 typedef struct MIPSGCRState MIPSGCRState; 18 DECLARE_INSTANCE_CHECKER(MIPSGCRState, MIPS_GCR, 19 TYPE_MIPS_GCR) 20 21 #define GCR_BASE_ADDR 0x1fbf8000ULL 22 #define GCR_ADDRSPACE_SZ 0x8000 23 24 /* Offsets to register blocks */ 25 #define MIPS_GCB_OFS 0x0000 /* Global Control Block */ 26 #define MIPS_CLCB_OFS 0x2000 /* Core Local Control Block */ 27 #define MIPS_COCB_OFS 0x4000 /* Core Other Control Block */ 28 #define MIPS_GDB_OFS 0x6000 /* Global Debug Block */ 29 30 /* Global Control Block Register Map */ 31 #define GCR_CONFIG_OFS 0x0000 32 #define GCR_BASE_OFS 0x0008 33 #define GCR_REV_OFS 0x0030 34 #define GCR_GIC_BASE_OFS 0x0080 35 #define GCR_CPC_BASE_OFS 0x0088 36 #define GCR_GIC_STATUS_OFS 0x00D0 37 #define GCR_CPC_STATUS_OFS 0x00F0 38 #define GCR_L2_CONFIG_OFS 0x0130 39 40 /* Core Local and Core Other Block Register Map */ 41 #define GCR_CL_CONFIG_OFS 0x0010 42 #define GCR_CL_OTHER_OFS 0x0018 43 #define GCR_CL_RESETBASE_OFS 0x0020 44 45 /* GCR_L2_CONFIG register fields */ 46 #define GCR_L2_CONFIG_BYPASS_SHF 20 47 #define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF) 48 49 /* GCR_BASE register fields */ 50 #define GCR_BASE_GCRBASE_MSK 0xffffffff8000ULL 51 52 /* GCR_GIC_BASE register fields */ 53 #define GCR_GIC_BASE_GICEN_MSK 1 54 #define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL 55 #define GCR_GIC_BASE_MSK (GCR_GIC_BASE_GICEN_MSK | GCR_GIC_BASE_GICBASE_MSK) 56 57 /* GCR_CPC_BASE register fields */ 58 #define GCR_CPC_BASE_CPCEN_MSK 1 59 #define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL 60 #define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MSK) 61 62 /* GCR_CL_OTHER_OFS register fields */ 63 #define GCR_CL_OTHER_VPOTHER_MSK 0x7 64 #define GCR_CL_OTHER_MSK GCR_CL_OTHER_VPOTHER_MSK 65 66 /* GCR_CL_RESETBASE_OFS register fields */ 67 #define GCR_CL_RESET_BASE_RESETBASE_MSK 0xFFFFF000U 68 #define GCR_CL_RESET_BASE_MSK GCR_CL_RESET_BASE_RESETBASE_MSK 69 70 typedef struct MIPSGCRVPState MIPSGCRVPState; 71 struct MIPSGCRVPState { 72 uint32_t other; 73 uint64_t reset_base; 74 }; 75 76 struct MIPSGCRState { 77 SysBusDevice parent_obj; 78 79 int32_t gcr_rev; 80 int32_t num_vps; 81 hwaddr gcr_base; 82 MemoryRegion iomem; 83 MemoryRegion *cpc_mr; 84 MemoryRegion *gic_mr; 85 86 uint64_t cpc_base; 87 uint64_t gic_base; 88 89 /* VP Local/Other Registers */ 90 MIPSGCRVPState *vps; 91 }; 92 93 #endif /* MIPS_CMGCR_H */ 94