1 /*
2  * Header file for the Xilinx Versal's PMC IOU SLCR
3  *
4  * Copyright (C) 2021 Xilinx Inc
5  * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  */
25 
26 /*
27  * This is a model of Xilinx Versal's PMC I/O Peripheral Control and Status
28  * module documented in Versal's Technical Reference manual [1] and the Versal
29  * ACAP Register reference [2].
30  *
31  * References:
32  *
33  * [1] Versal ACAP Technical Reference Manual,
34  *     https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
35  *
36  * [2] Versal ACAP Register Reference,
37  *     https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___pmc_iop_slcr.html
38  *
39  * QEMU interface:
40  * + sysbus MMIO region 0: MemoryRegion for the device's registers
41  * + sysbus IRQ 0: PMC (AXI and APB) parity error interrupt detected by the PMC
42  *   I/O peripherals.
43  * + sysbus IRQ 1: Device interrupt.
44  * + Named GPIO output "sd-emmc-sel[0]": Enables 0: SD mode or 1: eMMC mode on
45  *   SD/eMMC controller 0.
46  * + Named GPIO output "sd-emmc-sel[1]": Enables 0: SD mode or 1: eMMC mode on
47  *   SD/eMMC controller 1.
48  * + Named GPIO output "qspi-ospi-mux-sel": Selects 0: QSPI linear region or 1:
49  *   OSPI linear region.
50  * + Named GPIO output "ospi-mux-sel": Selects 0: OSPI Indirect access mode or
51  *   1: OSPI direct access mode.
52  */
53 
54 #ifndef XILINX_VERSAL_PMC_IOU_SLCR_H
55 #define XILINX_VERSAL_PMC_IOU_SLCR_H
56 
57 #include "hw/register.h"
58 
59 #define TYPE_XILINX_VERSAL_PMC_IOU_SLCR "xlnx.versal-pmc-iou-slcr"
60 
61 OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalPmcIouSlcr, XILINX_VERSAL_PMC_IOU_SLCR)
62 
63 #define XILINX_VERSAL_PMC_IOU_SLCR_R_MAX (0x828 / 4 + 1)
64 
65 struct XlnxVersalPmcIouSlcr {
66     SysBusDevice parent_obj;
67     MemoryRegion iomem;
68     qemu_irq irq_parity_imr;
69     qemu_irq irq_imr;
70     qemu_irq sd_emmc_sel[2];
71     qemu_irq qspi_ospi_mux_sel;
72     qemu_irq ospi_mux_sel;
73 
74     uint32_t regs[XILINX_VERSAL_PMC_IOU_SLCR_R_MAX];
75     RegisterInfo regs_info[XILINX_VERSAL_PMC_IOU_SLCR_R_MAX];
76 };
77 
78 #endif /* XILINX_VERSAL_PMC_IOU_SLCR_H */
79