1 /* 2 * QEMU model of ZynqMP APU Control. 3 * 4 * Copyright (c) 2013-2022 Xilinx Inc 5 * SPDX-License-Identifier: GPL-2.0-or-later 6 * 7 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and 8 * Edgar E. Iglesias <edgar.iglesias@xilinx.com> 9 * 10 */ 11 #ifndef HW_MISC_XLNX_ZYNQMP_APU_CTRL_H 12 #define HW_MISC_XLNX_ZYNQMP_APU_CTRL_H 13 14 #include "hw/sysbus.h" 15 #include "hw/register.h" 16 #include "target/arm/cpu-qom.h" 17 18 #define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl" 19 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL) 20 21 REG32(APU_ERR_CTRL, 0x0) 22 FIELD(APU_ERR_CTRL, PSLVERR, 0, 1) 23 REG32(ISR, 0x10) 24 FIELD(ISR, INV_APB, 0, 1) 25 REG32(IMR, 0x14) 26 FIELD(IMR, INV_APB, 0, 1) 27 REG32(IEN, 0x18) 28 FIELD(IEN, INV_APB, 0, 1) 29 REG32(IDS, 0x1c) 30 FIELD(IDS, INV_APB, 0, 1) 31 REG32(CONFIG_0, 0x20) 32 FIELD(CONFIG_0, CFGTE, 24, 4) 33 FIELD(CONFIG_0, CFGEND, 16, 4) 34 FIELD(CONFIG_0, VINITHI, 8, 4) 35 FIELD(CONFIG_0, AA64NAA32, 0, 4) 36 REG32(CONFIG_1, 0x24) 37 FIELD(CONFIG_1, L2RSTDISABLE, 29, 1) 38 FIELD(CONFIG_1, L1RSTDISABLE, 28, 1) 39 FIELD(CONFIG_1, CP15DISABLE, 0, 4) 40 REG32(RVBARADDR0L, 0x40) 41 FIELD(RVBARADDR0L, ADDR, 2, 30) 42 REG32(RVBARADDR0H, 0x44) 43 FIELD(RVBARADDR0H, ADDR, 0, 8) 44 REG32(RVBARADDR1L, 0x48) 45 FIELD(RVBARADDR1L, ADDR, 2, 30) 46 REG32(RVBARADDR1H, 0x4c) 47 FIELD(RVBARADDR1H, ADDR, 0, 8) 48 REG32(RVBARADDR2L, 0x50) 49 FIELD(RVBARADDR2L, ADDR, 2, 30) 50 REG32(RVBARADDR2H, 0x54) 51 FIELD(RVBARADDR2H, ADDR, 0, 8) 52 REG32(RVBARADDR3L, 0x58) 53 FIELD(RVBARADDR3L, ADDR, 2, 30) 54 REG32(RVBARADDR3H, 0x5c) 55 FIELD(RVBARADDR3H, ADDR, 0, 8) 56 REG32(ACE_CTRL, 0x60) 57 FIELD(ACE_CTRL, AWQOS, 16, 4) 58 FIELD(ACE_CTRL, ARQOS, 0, 4) 59 REG32(SNOOP_CTRL, 0x80) 60 FIELD(SNOOP_CTRL, ACE_INACT, 4, 1) 61 FIELD(SNOOP_CTRL, ACP_INACT, 0, 1) 62 REG32(PWRCTL, 0x90) 63 FIELD(PWRCTL, CLREXMONREQ, 17, 1) 64 FIELD(PWRCTL, L2FLUSHREQ, 16, 1) 65 FIELD(PWRCTL, CPUPWRDWNREQ, 0, 4) 66 REG32(PWRSTAT, 0x94) 67 FIELD(PWRSTAT, CLREXMONACK, 17, 1) 68 FIELD(PWRSTAT, L2FLUSHDONE, 16, 1) 69 FIELD(PWRSTAT, DBGNOPWRDWN, 0, 4) 70 71 #define APU_R_MAX ((R_PWRSTAT) + 1) 72 73 #define APU_MAX_CPU 4 74 75 struct XlnxZynqMPAPUCtrl { 76 SysBusDevice busdev; 77 78 ARMCPU *cpus[APU_MAX_CPU]; 79 /* WFIs towards PMU. */ 80 qemu_irq wfi_out[4]; 81 /* CPU Power status towards INTC Redirect. */ 82 qemu_irq cpu_power_status[4]; 83 qemu_irq irq_imr; 84 85 uint8_t cpu_pwrdwn_req; 86 uint8_t cpu_in_wfi; 87 88 RegisterInfoArray *reg_array; 89 uint32_t regs[APU_R_MAX]; 90 RegisterInfo regs_info[APU_R_MAX]; 91 }; 92 93 #endif 94