xref: /qemu/include/hw/net/npcm_gmac.h (revision 7c0dfcf9) 
1 /*
2  * Nuvoton NPCM7xx/8xx GMAC Module
3  *
4  * Copyright 2024 Google LLC
5  * Authors:
6  * Hao Wu <wuhaotsh@google.com>
7  * Nabih Estefan <nabihestefan@google.com>
8  *
9  * This program is free software; you can redistribute it and/or modify it
10  * under the terms of the GNU General Public License as published by the
11  * Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17  * for more details.
18  */
19 
20 #ifndef NPCM_GMAC_H
21 #define NPCM_GMAC_H
22 
23 #include "hw/irq.h"
24 #include "hw/sysbus.h"
25 #include "net/net.h"
26 
27 #define NPCM_GMAC_NR_REGS (0x1060 / sizeof(uint32_t))
28 
29 #define NPCM_GMAC_MAX_PHYS 32
30 #define NPCM_GMAC_MAX_PHY_REGS 32
31 
32 struct NPCMGMACRxDesc {
33     uint32_t rdes0;
34     uint32_t rdes1;
35     uint32_t rdes2;
36     uint32_t rdes3;
37 };
38 
39 /* NPCMGMACRxDesc.flags values */
40 /* RDES2 and RDES3 are buffer addresses */
41 /* Owner: 0 = software, 1 = dma */
42 #define RX_DESC_RDES0_OWN BIT(31)
43 /* Destination Address Filter Fail */
44 #define RX_DESC_RDES0_DEST_ADDR_FILT_FAIL BIT(30)
45 /* Frame length */
46 #define RX_DESC_RDES0_FRAME_LEN_MASK(word) extract32(word, 16, 14)
47 /* Frame length Shift*/
48 #define RX_DESC_RDES0_FRAME_LEN_SHIFT 16
49 /* Error Summary */
50 #define RX_DESC_RDES0_ERR_SUMM_MASK BIT(15)
51 /* Descriptor Error */
52 #define RX_DESC_RDES0_DESC_ERR_MASK BIT(14)
53 /* Source Address Filter Fail */
54 #define RX_DESC_RDES0_SRC_ADDR_FILT_FAIL_MASK BIT(13)
55 /* Length Error */
56 #define RX_DESC_RDES0_LEN_ERR_MASK BIT(12)
57 /* Overflow Error */
58 #define RX_DESC_RDES0_OVRFLW_ERR_MASK BIT(11)
59 /* VLAN Tag */
60 #define RX_DESC_RDES0_VLAN_TAG_MASK BIT(10)
61 /* First Descriptor */
62 #define RX_DESC_RDES0_FIRST_DESC_MASK BIT(9)
63 /* Last Descriptor */
64 #define RX_DESC_RDES0_LAST_DESC_MASK BIT(8)
65 /* IPC Checksum Error/Giant Frame */
66 #define RX_DESC_RDES0_IPC_CHKSM_ERR_GNT_FRM_MASK BIT(7)
67 /* Late Collision */
68 #define RX_DESC_RDES0_LT_COLL_MASK BIT(6)
69 /* Frame Type */
70 #define RX_DESC_RDES0_FRM_TYPE_MASK BIT(5)
71 /* Receive Watchdog Timeout */
72 #define RX_DESC_RDES0_REC_WTCHDG_TMT_MASK BIT(4)
73 /* Receive Error */
74 #define RX_DESC_RDES0_RCV_ERR_MASK BIT(3)
75 /* Dribble Bit Error */
76 #define RX_DESC_RDES0_DRBL_BIT_ERR_MASK BIT(2)
77 /* Cyclcic Redundancy Check Error */
78 #define RX_DESC_RDES0_CRC_ERR_MASK BIT(1)
79 /* Rx MAC Address/Payload Checksum Error */
80 #define RC_DESC_RDES0_RCE_MASK BIT(0)
81 
82 /* Disable Interrupt on Completion */
83 #define RX_DESC_RDES1_DIS_INTR_COMP_MASK BIT(31)
84 /* Recieve end of ring */
85 #define RX_DESC_RDES1_RC_END_RING_MASK BIT(25)
86 /* Second Address Chained */
87 #define RX_DESC_RDES1_SEC_ADDR_CHND_MASK BIT(24)
88 /* Receive Buffer 2 Size */
89 #define RX_DESC_RDES1_BFFR2_SZ_SHIFT 11
90 #define RX_DESC_RDES1_BFFR2_SZ_MASK(word) extract32(word, \
91     RX_DESC_RDES1_BFFR2_SZ_SHIFT, 11)
92 /* Receive Buffer 1 Size */
93 #define RX_DESC_RDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 11)
94 
95 
96 struct NPCMGMACTxDesc {
97     uint32_t tdes0;
98     uint32_t tdes1;
99     uint32_t tdes2;
100     uint32_t tdes3;
101 };
102 
103 /* NPCMGMACTxDesc.flags values */
104 /* TDES2 and TDES3 are buffer addresses */
105 /* Owner: 0 = software, 1 = gmac */
106 #define TX_DESC_TDES0_OWN BIT(31)
107 /* Tx Time Stamp Status */
108 #define TX_DESC_TDES0_TTSS_MASK BIT(17)
109 /* IP Header Error */
110 #define TX_DESC_TDES0_IP_HEAD_ERR_MASK BIT(16)
111 /* Error Summary */
112 #define TX_DESC_TDES0_ERR_SUMM_MASK BIT(15)
113 /* Jabber Timeout */
114 #define TX_DESC_TDES0_JBBR_TMT_MASK BIT(14)
115 /* Frame Flushed */
116 #define TX_DESC_TDES0_FRM_FLSHD_MASK BIT(13)
117 /* Payload Checksum Error */
118 #define TX_DESC_TDES0_PYLD_CHKSM_ERR_MASK BIT(12)
119 /* Loss of Carrier */
120 #define TX_DESC_TDES0_LSS_CARR_MASK BIT(11)
121 /* No Carrier */
122 #define TX_DESC_TDES0_NO_CARR_MASK BIT(10)
123 /* Late Collision */
124 #define TX_DESC_TDES0_LATE_COLL_MASK BIT(9)
125 /* Excessive Collision */
126 #define TX_DESC_TDES0_EXCS_COLL_MASK BIT(8)
127 /* VLAN Frame */
128 #define TX_DESC_TDES0_VLAN_FRM_MASK BIT(7)
129 /* Collision Count */
130 #define TX_DESC_TDES0_COLL_CNT_MASK(word) extract32(word, 3, 4)
131 /* Excessive Deferral */
132 #define TX_DESC_TDES0_EXCS_DEF_MASK BIT(2)
133 /* Underflow Error */
134 #define TX_DESC_TDES0_UNDRFLW_ERR_MASK BIT(1)
135 /* Deferred Bit */
136 #define TX_DESC_TDES0_DFRD_BIT_MASK BIT(0)
137 
138 /* Interrupt of Completion */
139 #define TX_DESC_TDES1_INTERR_COMP_MASK BIT(31)
140 /* Last Segment */
141 #define TX_DESC_TDES1_LAST_SEG_MASK BIT(30)
142 /* First Segment */
143 #define TX_DESC_TDES1_FIRST_SEG_MASK BIT(29)
144 /* Checksum Insertion Control */
145 #define TX_DESC_TDES1_CHKSM_INS_CTRL_MASK(word) extract32(word, 27, 2)
146 /* Disable Cyclic Redundancy Check */
147 #define TX_DESC_TDES1_DIS_CDC_MASK BIT(26)
148 /* Transmit End of Ring */
149 #define TX_DESC_TDES1_TX_END_RING_MASK BIT(25)
150 /* Secondary Address Chained */
151 #define TX_DESC_TDES1_SEC_ADDR_CHND_MASK BIT(24)
152 /* Transmit Buffer 2 Size */
153 #define TX_DESC_TDES1_BFFR2_SZ_MASK(word) extract32(word, 11, 11)
154 /* Transmit Buffer 1 Size */
155 #define TX_DESC_TDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 11)
156 
157 typedef struct NPCMGMACState {
158     SysBusDevice parent;
159 
160     MemoryRegion iomem;
161     qemu_irq irq;
162 
163     NICState *nic;
164     NICConf conf;
165 
166     uint32_t regs[NPCM_GMAC_NR_REGS];
167     uint16_t phy_regs[NPCM_GMAC_MAX_PHYS][NPCM_GMAC_MAX_PHY_REGS];
168 } NPCMGMACState;
169 
170 #define TYPE_NPCM_GMAC "npcm-gmac"
171 OBJECT_DECLARE_SIMPLE_TYPE(NPCMGMACState, NPCM_GMAC)
172 
173 /* Mask for RO bits in Status */
174 #define NPCM_DMA_STATUS_RO_MASK(word) (word & 0xfffe0000)
175 /* Mask for RO bits in Status */
176 #define NPCM_DMA_STATUS_W1C_MASK(word) (word & 0x1e7ff)
177 
178 /* Transmit Process State */
179 #define NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT 20
180 /* Transmit States */
181 #define NPCM_DMA_STATUS_TX_STOPPED_STATE \
182     (0b000)
183 #define NPCM_DMA_STATUS_TX_RUNNING_FETCHING_STATE \
184     (0b001)
185 #define NPCM_DMA_STATUS_TX_RUNNING_WAITING_STATE \
186     (0b010)
187 #define NPCM_DMA_STATUS_TX_RUNNING_READ_STATE \
188     (0b011)
189 #define NPCM_DMA_STATUS_TX_SUSPENDED_STATE \
190     (0b110)
191 #define NPCM_DMA_STATUS_TX_RUNNING_CLOSING_STATE \
192     (0b111)
193 /* Transmit Process State */
194 #define NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT 17
195 /* Receive States */
196 #define NPCM_DMA_STATUS_RX_STOPPED_STATE \
197     (0b000)
198 #define NPCM_DMA_STATUS_RX_RUNNING_FETCHING_STATE \
199     (0b001)
200 #define NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE \
201     (0b011)
202 #define NPCM_DMA_STATUS_RX_SUSPENDED_STATE \
203     (0b100)
204 #define NPCM_DMA_STATUS_RX_RUNNING_CLOSING_STATE \
205     (0b101)
206 #define NPCM_DMA_STATUS_RX_RUNNING_TRANSFERRING_STATE \
207     (0b111)
208 
209 
210 /* Early Receive Interrupt */
211 #define NPCM_DMA_STATUS_ERI BIT(14)
212 /* Fatal Bus Error Interrupt */
213 #define NPCM_DMA_STATUS_FBI BIT(13)
214 /* Early transmit Interrupt */
215 #define NPCM_DMA_STATUS_ETI BIT(10)
216 /* Receive Watchdog Timout */
217 #define NPCM_DMA_STATUS_RWT BIT(9)
218 /* Receive Process Stopped */
219 #define NPCM_DMA_STATUS_RPS BIT(8)
220 /* Receive Buffer Unavailable */
221 #define NPCM_DMA_STATUS_RU BIT(7)
222 /* Receive Interrupt */
223 #define NPCM_DMA_STATUS_RI BIT(6)
224 /* Transmit Underflow */
225 #define NPCM_DMA_STATUS_UNF BIT(5)
226 /* Receive Overflow */
227 #define NPCM_DMA_STATUS_OVF BIT(4)
228 /* Transmit Jabber Timeout */
229 #define NPCM_DMA_STATUS_TJT BIT(3)
230 /* Transmit Buffer Unavailable */
231 #define NPCM_DMA_STATUS_TU BIT(2)
232 /* Transmit Process Stopped */
233 #define NPCM_DMA_STATUS_TPS BIT(1)
234 /* Transmit Interrupt */
235 #define NPCM_DMA_STATUS_TI BIT(0)
236 
237 /* Normal Interrupt Summary */
238 #define NPCM_DMA_STATUS_NIS BIT(16)
239 /* Interrupts enabled by NIE */
240 #define NPCM_DMA_STATUS_NIS_BITS (NPCM_DMA_STATUS_TI | \
241                                   NPCM_DMA_STATUS_TU | \
242                                   NPCM_DMA_STATUS_RI | \
243                                   NPCM_DMA_STATUS_ERI)
244 /* Abnormal Interrupt Summary */
245 #define NPCM_DMA_STATUS_AIS BIT(15)
246 /* Interrupts enabled by AIE */
247 #define NPCM_DMA_STATUS_AIS_BITS (NPCM_DMA_STATUS_TPS | \
248                                   NPCM_DMA_STATUS_TJT | \
249                                   NPCM_DMA_STATUS_OVF | \
250                                   NPCM_DMA_STATUS_UNF | \
251                                   NPCM_DMA_STATUS_RU  | \
252                                   NPCM_DMA_STATUS_RPS | \
253                                   NPCM_DMA_STATUS_RWT | \
254                                   NPCM_DMA_STATUS_ETI | \
255                                   NPCM_DMA_STATUS_FBI)
256 
257 /* Early Receive Interrupt Enable */
258 #define NPCM_DMA_INTR_ENAB_ERE BIT(14)
259 /* Fatal Bus Error Interrupt Enable */
260 #define NPCM_DMA_INTR_ENAB_FBE BIT(13)
261 /* Early transmit Interrupt Enable */
262 #define NPCM_DMA_INTR_ENAB_ETE BIT(10)
263 /* Receive Watchdog Timout Enable */
264 #define NPCM_DMA_INTR_ENAB_RWE BIT(9)
265 /* Receive Process Stopped Enable */
266 #define NPCM_DMA_INTR_ENAB_RSE BIT(8)
267 /* Receive Buffer Unavailable Enable */
268 #define NPCM_DMA_INTR_ENAB_RUE BIT(7)
269 /* Receive Interrupt Enable */
270 #define NPCM_DMA_INTR_ENAB_RIE BIT(6)
271 /* Transmit Underflow Enable */
272 #define NPCM_DMA_INTR_ENAB_UNE BIT(5)
273 /* Receive Overflow Enable */
274 #define NPCM_DMA_INTR_ENAB_OVE BIT(4)
275 /* Transmit Jabber Timeout Enable */
276 #define NPCM_DMA_INTR_ENAB_TJE BIT(3)
277 /* Transmit Buffer Unavailable Enable */
278 #define NPCM_DMA_INTR_ENAB_TUE BIT(2)
279 /* Transmit Process Stopped Enable */
280 #define NPCM_DMA_INTR_ENAB_TSE BIT(1)
281 /* Transmit Interrupt Enable */
282 #define NPCM_DMA_INTR_ENAB_TIE BIT(0)
283 
284 /* Normal Interrupt Summary Enable */
285 #define NPCM_DMA_INTR_ENAB_NIE BIT(16)
286 /* Interrupts enabled by NIE Enable */
287 #define NPCM_DMA_INTR_ENAB_NIE_BITS (NPCM_DMA_INTR_ENAB_TIE | \
288                                      NPCM_DMA_INTR_ENAB_TUE | \
289                                      NPCM_DMA_INTR_ENAB_RIE | \
290                                      NPCM_DMA_INTR_ENAB_ERE)
291 /* Abnormal Interrupt Summary Enable */
292 #define NPCM_DMA_INTR_ENAB_AIE BIT(15)
293 /* Interrupts enabled by AIE Enable */
294 #define NPCM_DMA_INTR_ENAB_AIE_BITS (NPCM_DMA_INTR_ENAB_TSE | \
295                                      NPCM_DMA_INTR_ENAB_TJE | \
296                                      NPCM_DMA_INTR_ENAB_OVE | \
297                                      NPCM_DMA_INTR_ENAB_UNE | \
298                                      NPCM_DMA_INTR_ENAB_RUE | \
299                                      NPCM_DMA_INTR_ENAB_RSE | \
300                                      NPCM_DMA_INTR_ENAB_RWE | \
301                                      NPCM_DMA_INTR_ENAB_ETE | \
302                                      NPCM_DMA_INTR_ENAB_FBE)
303 
304 /* Flushing Disabled */
305 #define NPCM_DMA_CONTROL_FLUSH_MASK BIT(24)
306 /* Start/stop Transmit */
307 #define NPCM_DMA_CONTROL_START_STOP_TX BIT(13)
308 /* Start/stop Receive */
309 #define NPCM_DMA_CONTROL_START_STOP_RX BIT(1)
310 /* Next receive descriptor start address */
311 #define NPCM_DMA_HOST_RX_DESC_MASK(word) ((uint32_t) (word) & ~3u)
312 /* Next transmit descriptor start address */
313 #define NPCM_DMA_HOST_TX_DESC_MASK(word) ((uint32_t) (word) & ~3u)
314 
315 /* Receive enable */
316 #define NPCM_GMAC_MAC_CONFIG_RX_EN BIT(2)
317 /* Transmit enable */
318 #define NPCM_GMAC_MAC_CONFIG_TX_EN BIT(3)
319 
320 /* Frame Receive All */
321 #define NPCM_GMAC_FRAME_FILTER_REC_ALL_MASK BIT(31)
322 /* Frame HPF Filter*/
323 #define NPCM_GMAC_FRAME_FILTER_HPF_MASK BIT(10)
324 /* Frame SAF Filter*/
325 #define NPCM_GMAC_FRAME_FILTER_SAF_MASK BIT(9)
326 /* Frame SAIF Filter*/
327 #define NPCM_GMAC_FRAME_FILTER_SAIF_MASK BIT(8)
328 /* Frame PCF Filter*/
329 #define NPCM_GMAC_FRAME_FILTER_PCF_MASK BIT(word) extract32((word), 6, 2)
330 /* Frame DBF Filter*/
331 #define NPCM_GMAC_FRAME_FILTER_DBF_MASK BIT(5)
332 /* Frame PM Filter*/
333 #define NPCM_GMAC_FRAME_FILTER_PM_MASK BIT(4)
334 /* Frame DAIF Filter*/
335 #define NPCM_GMAC_FRAME_FILTER_DAIF_MASK BIT(3)
336 /* Frame HMC Filter*/
337 #define NPCM_GMAC_FRAME_FILTER_HMC_MASK BIT(2)
338 /* Frame HUC Filter*/
339 #define NPCM_GMAC_FRAME_FILTER_HUC_MASK BIT(1)
340 /* Frame PR Filter*/
341 #define NPCM_GMAC_FRAME_FILTER_PR_MASK BIT(0)
342 
343 #endif /* NPCM_GMAC_H */
344