1e029bb00SHelge Deller /* 2e029bb00SHelge Deller * HP-PARISC Astro Bus connector with Elroy PCI host bridges 3e029bb00SHelge Deller */ 4e029bb00SHelge Deller 5e029bb00SHelge Deller #ifndef ASTRO_H 6e029bb00SHelge Deller #define ASTRO_H 7e029bb00SHelge Deller 8e029bb00SHelge Deller #include "hw/pci/pci_host.h" 9e029bb00SHelge Deller 10e029bb00SHelge Deller #define ASTRO_HPA 0xfed00000 11e029bb00SHelge Deller 12e029bb00SHelge Deller #define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */ 13e029bb00SHelge Deller 14e029bb00SHelge Deller #define TYPE_ASTRO_CHIP "astro-chip" 15e029bb00SHelge Deller OBJECT_DECLARE_SIMPLE_TYPE(AstroState, ASTRO_CHIP) 16e029bb00SHelge Deller 17e029bb00SHelge Deller #define TYPE_ELROY_PCI_HOST_BRIDGE "elroy-pcihost" 18e029bb00SHelge Deller OBJECT_DECLARE_SIMPLE_TYPE(ElroyState, ELROY_PCI_HOST_BRIDGE) 19e029bb00SHelge Deller 20e029bb00SHelge Deller #define ELROY_NUM 4 /* # of Elroys */ 21e029bb00SHelge Deller #define ELROY_IRQS 8 /* IOSAPIC IRQs */ 22e029bb00SHelge Deller 23e029bb00SHelge Deller /* ASTRO Memory and I/O regions */ 24e029bb00SHelge Deller #define LMMIO_DIST_BASE_ADDR 0xf4000000ULL 25e029bb00SHelge Deller #define LMMIO_DIST_BASE_SIZE 0x4000000ULL 26e029bb00SHelge Deller 27e029bb00SHelge Deller #define IOS_DIST_BASE_ADDR 0xfffee00000ULL 28e029bb00SHelge Deller #define IOS_DIST_BASE_SIZE 0x10000ULL 29e029bb00SHelge Deller 30*f410b688SHelge Deller #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */ 31*f410b688SHelge Deller 32e029bb00SHelge Deller struct AstroState; 33e029bb00SHelge Deller 34e029bb00SHelge Deller struct ElroyState { 35e029bb00SHelge Deller PCIHostState parent_obj; 36e029bb00SHelge Deller 37e029bb00SHelge Deller /* parent Astro device */ 38e029bb00SHelge Deller struct AstroState *astro; 39e029bb00SHelge Deller 40e029bb00SHelge Deller /* HPA of this Elroy */ 41e029bb00SHelge Deller hwaddr hpa; 42e029bb00SHelge Deller 43e029bb00SHelge Deller /* PCI bus number (Elroy number) */ 44e029bb00SHelge Deller unsigned int pci_bus_num; 45e029bb00SHelge Deller 46e029bb00SHelge Deller uint64_t config_address; 47e029bb00SHelge Deller uint64_t config_reg_elroy; 48e029bb00SHelge Deller 49e029bb00SHelge Deller uint64_t status_control; 50e029bb00SHelge Deller uint64_t arb_mask; 51e029bb00SHelge Deller uint64_t mmio_base[(0x0250 - 0x200) / 8]; 52e029bb00SHelge Deller uint64_t error_config; 53e029bb00SHelge Deller 54e029bb00SHelge Deller uint32_t iosapic_reg_select; 55e029bb00SHelge Deller uint64_t iosapic_reg[0x20]; 56e029bb00SHelge Deller 57e029bb00SHelge Deller uint32_t ilr; 58e029bb00SHelge Deller 59e029bb00SHelge Deller MemoryRegion this_mem; 60e029bb00SHelge Deller 61e029bb00SHelge Deller MemoryRegion pci_mmio; 62e029bb00SHelge Deller MemoryRegion pci_mmio_alias; 63e029bb00SHelge Deller MemoryRegion pci_hole; 64e029bb00SHelge Deller MemoryRegion pci_io; 65e029bb00SHelge Deller }; 66e029bb00SHelge Deller 67e029bb00SHelge Deller struct AstroState { 68e029bb00SHelge Deller PCIHostState parent_obj; 69e029bb00SHelge Deller 70e029bb00SHelge Deller uint64_t ioc_ctrl; 71e029bb00SHelge Deller uint64_t ioc_status_ctrl; 72e029bb00SHelge Deller uint64_t ioc_ranges[(0x03d8 - 0x300) / 8]; 73e029bb00SHelge Deller uint64_t ioc_rope_config; 74e029bb00SHelge Deller uint64_t ioc_status_control; 75e029bb00SHelge Deller uint64_t ioc_flush_control; 76e029bb00SHelge Deller uint64_t ioc_rope_control[8]; 77e029bb00SHelge Deller uint64_t tlb_ibase; 78e029bb00SHelge Deller uint64_t tlb_imask; 79e029bb00SHelge Deller uint64_t tlb_pcom; 80e029bb00SHelge Deller uint64_t tlb_tcnfg; 81e029bb00SHelge Deller uint64_t tlb_pdir_base; 82e029bb00SHelge Deller 83e029bb00SHelge Deller struct ElroyState *elroy[ELROY_NUM]; 84e029bb00SHelge Deller 85e029bb00SHelge Deller MemoryRegion this_mem; 86e029bb00SHelge Deller 87e029bb00SHelge Deller MemoryRegion pci_mmio; 88e029bb00SHelge Deller MemoryRegion pci_io; 89e029bb00SHelge Deller 90e029bb00SHelge Deller IOMMUMemoryRegion iommu; 91e029bb00SHelge Deller AddressSpace iommu_as; 92e029bb00SHelge Deller }; 93e029bb00SHelge Deller 94e029bb00SHelge Deller #endif 95