10db9350eSMark Cave-Ayland /* 2a1a62cedSMichael Tokarev * HP-PARISC Dino PCI chipset emulation, as in B160L and similar machines 30db9350eSMark Cave-Ayland * 40db9350eSMark Cave-Ayland * (C) 2017-2019 by Helge Deller <deller@gmx.de> 50db9350eSMark Cave-Ayland * 60db9350eSMark Cave-Ayland * This work is licensed under the GNU GPL license version 2 or later. 70db9350eSMark Cave-Ayland * 80db9350eSMark Cave-Ayland * Documentation available at: 90db9350eSMark Cave-Ayland * https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf 100db9350eSMark Cave-Ayland * https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf 110db9350eSMark Cave-Ayland */ 120db9350eSMark Cave-Ayland 130db9350eSMark Cave-Ayland #ifndef DINO_H 140db9350eSMark Cave-Ayland #define DINO_H 150db9350eSMark Cave-Ayland 160db9350eSMark Cave-Ayland #include "hw/pci/pci_host.h" 170db9350eSMark Cave-Ayland 180db9350eSMark Cave-Ayland #define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost" 190db9350eSMark Cave-Ayland OBJECT_DECLARE_SIMPLE_TYPE(DinoState, DINO_PCI_HOST_BRIDGE) 200db9350eSMark Cave-Ayland 210db9350eSMark Cave-Ayland #define DINO_IAR0 0x004 220db9350eSMark Cave-Ayland #define DINO_IODC 0x008 230db9350eSMark Cave-Ayland #define DINO_IRR0 0x00C /* RO */ 240db9350eSMark Cave-Ayland #define DINO_IAR1 0x010 250db9350eSMark Cave-Ayland #define DINO_IRR1 0x014 /* RO */ 260db9350eSMark Cave-Ayland #define DINO_IMR 0x018 270db9350eSMark Cave-Ayland #define DINO_IPR 0x01C 280db9350eSMark Cave-Ayland #define DINO_TOC_ADDR 0x020 290db9350eSMark Cave-Ayland #define DINO_ICR 0x024 300db9350eSMark Cave-Ayland #define DINO_ILR 0x028 /* RO */ 310db9350eSMark Cave-Ayland #define DINO_IO_COMMAND 0x030 /* WO */ 320db9350eSMark Cave-Ayland #define DINO_IO_STATUS 0x034 /* RO */ 330db9350eSMark Cave-Ayland #define DINO_IO_CONTROL 0x038 340db9350eSMark Cave-Ayland #define DINO_IO_GSC_ERR_RESP 0x040 /* RO */ 350db9350eSMark Cave-Ayland #define DINO_IO_ERR_INFO 0x044 /* RO */ 360db9350eSMark Cave-Ayland #define DINO_IO_PCI_ERR_RESP 0x048 /* RO */ 370db9350eSMark Cave-Ayland #define DINO_IO_FBB_EN 0x05c 380db9350eSMark Cave-Ayland #define DINO_IO_ADDR_EN 0x060 390db9350eSMark Cave-Ayland #define DINO_PCI_CONFIG_ADDR 0x064 400db9350eSMark Cave-Ayland #define DINO_PCI_CONFIG_DATA 0x068 410db9350eSMark Cave-Ayland #define DINO_PCI_IO_DATA 0x06c 420db9350eSMark Cave-Ayland #define DINO_PCI_MEM_DATA 0x070 /* Dino 3.x only */ 430db9350eSMark Cave-Ayland #define DINO_GSC2X_CONFIG 0x7b4 /* RO */ 440db9350eSMark Cave-Ayland #define DINO_GMASK 0x800 450db9350eSMark Cave-Ayland #define DINO_PAMR 0x804 460db9350eSMark Cave-Ayland #define DINO_PAPR 0x808 470db9350eSMark Cave-Ayland #define DINO_DAMODE 0x80c 480db9350eSMark Cave-Ayland #define DINO_PCICMD 0x810 490db9350eSMark Cave-Ayland #define DINO_PCISTS 0x814 /* R/WC */ 500db9350eSMark Cave-Ayland #define DINO_MLTIM 0x81c 510db9350eSMark Cave-Ayland #define DINO_BRDG_FEAT 0x820 520db9350eSMark Cave-Ayland #define DINO_PCIROR 0x824 530db9350eSMark Cave-Ayland #define DINO_PCIWOR 0x828 540db9350eSMark Cave-Ayland #define DINO_TLTIM 0x830 550db9350eSMark Cave-Ayland 560db9350eSMark Cave-Ayland #define DINO_IRQS 11 /* bits 0-10 are architected */ 570db9350eSMark Cave-Ayland #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ 580db9350eSMark Cave-Ayland #define DINO_LOCAL_IRQS (DINO_IRQS + 1) 590db9350eSMark Cave-Ayland #define DINO_MASK_IRQ(x) (1 << (x)) 600db9350eSMark Cave-Ayland 610db9350eSMark Cave-Ayland #define DINO_IRQ_PCIINTA 0 620db9350eSMark Cave-Ayland #define DINO_IRQ_PCIINTB 1 630db9350eSMark Cave-Ayland #define DINO_IRQ_PCIINTC 2 640db9350eSMark Cave-Ayland #define DINO_IRQ_PCIINTD 3 650db9350eSMark Cave-Ayland #define DINO_IRQ_PCIINTE 4 660db9350eSMark Cave-Ayland #define DINO_IRQ_PCIINTF 5 670db9350eSMark Cave-Ayland #define DINO_IRQ_GSCEXTINT 6 680db9350eSMark Cave-Ayland #define DINO_IRQ_BUSERRINT 7 690db9350eSMark Cave-Ayland #define DINO_IRQ_PS2INT 8 700db9350eSMark Cave-Ayland #define DINO_IRQ_UNUSED 9 710db9350eSMark Cave-Ayland #define DINO_IRQ_RS232INT 10 720db9350eSMark Cave-Ayland 730db9350eSMark Cave-Ayland #define PCIINTA 0x001 740db9350eSMark Cave-Ayland #define PCIINTB 0x002 750db9350eSMark Cave-Ayland #define PCIINTC 0x004 760db9350eSMark Cave-Ayland #define PCIINTD 0x008 770db9350eSMark Cave-Ayland #define PCIINTE 0x010 780db9350eSMark Cave-Ayland #define PCIINTF 0x020 790db9350eSMark Cave-Ayland #define GSCEXTINT 0x040 800db9350eSMark Cave-Ayland /* #define xxx 0x080 - bit 7 is "default" */ 810db9350eSMark Cave-Ayland /* #define xxx 0x100 - bit 8 not used */ 820db9350eSMark Cave-Ayland /* #define xxx 0x200 - bit 9 not used */ 830db9350eSMark Cave-Ayland #define RS232INT 0x400 840db9350eSMark Cave-Ayland 850db9350eSMark Cave-Ayland #define DINO_MEM_CHUNK_SIZE (8 * MiB) 860db9350eSMark Cave-Ayland 870db9350eSMark Cave-Ayland #define DINO800_REGS (1 + (DINO_TLTIM - DINO_GMASK) / 4) 880db9350eSMark Cave-Ayland static const uint32_t reg800_keep_bits[DINO800_REGS] = { 890db9350eSMark Cave-Ayland MAKE_64BIT_MASK(0, 1), /* GMASK */ 900db9350eSMark Cave-Ayland MAKE_64BIT_MASK(0, 7), /* PAMR */ 910db9350eSMark Cave-Ayland MAKE_64BIT_MASK(0, 7), /* PAPR */ 920db9350eSMark Cave-Ayland MAKE_64BIT_MASK(0, 8), /* DAMODE */ 930db9350eSMark Cave-Ayland MAKE_64BIT_MASK(0, 7), /* PCICMD */ 940db9350eSMark Cave-Ayland MAKE_64BIT_MASK(0, 9), /* PCISTS */ 950db9350eSMark Cave-Ayland MAKE_64BIT_MASK(0, 32), /* Undefined */ 960db9350eSMark Cave-Ayland MAKE_64BIT_MASK(0, 8), /* MLTIM */ 970db9350eSMark Cave-Ayland MAKE_64BIT_MASK(0, 30), /* BRDG_FEAT */ 980db9350eSMark Cave-Ayland MAKE_64BIT_MASK(0, 24), /* PCIROR */ 990db9350eSMark Cave-Ayland MAKE_64BIT_MASK(0, 22), /* PCIWOR */ 1000db9350eSMark Cave-Ayland MAKE_64BIT_MASK(0, 32), /* Undocumented */ 1010db9350eSMark Cave-Ayland MAKE_64BIT_MASK(0, 9), /* TLTIM */ 1020db9350eSMark Cave-Ayland }; 1030db9350eSMark Cave-Ayland 1040db9350eSMark Cave-Ayland /* offsets to DINO HPA: */ 1050db9350eSMark Cave-Ayland #define DINO_PCI_ADDR 0x064 1060db9350eSMark Cave-Ayland #define DINO_CONFIG_DATA 0x068 1070db9350eSMark Cave-Ayland #define DINO_IO_DATA 0x06c 1080db9350eSMark Cave-Ayland 1090db9350eSMark Cave-Ayland struct DinoState { 1100db9350eSMark Cave-Ayland PCIHostState parent_obj; 1110db9350eSMark Cave-Ayland 1120db9350eSMark Cave-Ayland /* 1130db9350eSMark Cave-Ayland * PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops, 1140db9350eSMark Cave-Ayland * so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops. 1150db9350eSMark Cave-Ayland */ 1160db9350eSMark Cave-Ayland uint32_t config_reg_dino; /* keep original copy, including 2 lowest bits */ 1170db9350eSMark Cave-Ayland 1180db9350eSMark Cave-Ayland uint32_t iar0; 1190db9350eSMark Cave-Ayland uint32_t iar1; 1200db9350eSMark Cave-Ayland uint32_t imr; 1210db9350eSMark Cave-Ayland uint32_t ipr; 1220db9350eSMark Cave-Ayland uint32_t icr; 1230db9350eSMark Cave-Ayland uint32_t ilr; 1240db9350eSMark Cave-Ayland uint32_t io_fbb_en; 1250db9350eSMark Cave-Ayland uint32_t io_addr_en; 1260db9350eSMark Cave-Ayland uint32_t io_control; 1270db9350eSMark Cave-Ayland uint32_t toc_addr; 1280db9350eSMark Cave-Ayland 1290db9350eSMark Cave-Ayland uint32_t reg800[DINO800_REGS]; 1300db9350eSMark Cave-Ayland 1310db9350eSMark Cave-Ayland MemoryRegion this_mem; 1320db9350eSMark Cave-Ayland MemoryRegion pci_mem; 1330db9350eSMark Cave-Ayland MemoryRegion pci_mem_alias[32]; 1340db9350eSMark Cave-Ayland 1350db9350eSMark Cave-Ayland MemoryRegion *memory_as; 1360db9350eSMark Cave-Ayland 1370db9350eSMark Cave-Ayland AddressSpace bm_as; 1380db9350eSMark Cave-Ayland MemoryRegion bm; 1390db9350eSMark Cave-Ayland MemoryRegion bm_ram_alias; 1400db9350eSMark Cave-Ayland MemoryRegion bm_pci_alias; 1410db9350eSMark Cave-Ayland MemoryRegion bm_cpu_alias; 1420db9350eSMark Cave-Ayland 1430db9350eSMark Cave-Ayland qemu_irq irqs[DINO_IRQS]; 1440db9350eSMark Cave-Ayland }; 1450db9350eSMark Cave-Ayland 1460db9350eSMark Cave-Ayland #endif 147