1 /* 2 * QEMU PowerPC PowerNV (POWER8) PHB3 model 3 * 4 * Copyright (c) 2013-2020, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PCI_HOST_PNV_PHB3_REGS_H 11 #define PCI_HOST_PNV_PHB3_REGS_H 12 13 #include "qemu/host-utils.h" 14 15 /* 16 * QEMU version of the GETFIELD/SETFIELD macros 17 * 18 * These are common with the PnvXive model. 19 */ 20 static inline uint64_t GETFIELD(uint64_t mask, uint64_t word) 21 { 22 return (word & mask) >> ctz64(mask); 23 } 24 25 static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, 26 uint64_t value) 27 { 28 return (word & ~mask) | ((value << ctz64(mask)) & mask); 29 } 30 31 /* 32 * PBCQ XSCOM registers 33 */ 34 35 #define PBCQ_NEST_IRSN_COMPARE 0x1a 36 #define PBCQ_NEST_IRSN_COMP PPC_BITMASK(0, 18) 37 #define PBCQ_NEST_IRSN_MASK 0x1b 38 #define PBCQ_NEST_LSI_SRC_ID 0x1f 39 #define PBCQ_NEST_LSI_SRC PPC_BITMASK(0, 7) 40 #define PBCQ_NEST_REGS_COUNT 0x46 41 #define PBCQ_NEST_MMIO_BAR0 0x40 42 #define PBCQ_NEST_MMIO_BAR1 0x41 43 #define PBCQ_NEST_PHB_BAR 0x42 44 #define PBCQ_NEST_MMIO_MASK0 0x43 45 #define PBCQ_NEST_MMIO_MASK1 0x44 46 #define PBCQ_NEST_BAR_EN 0x45 47 #define PBCQ_NEST_BAR_EN_MMIO0 PPC_BIT(0) 48 #define PBCQ_NEST_BAR_EN_MMIO1 PPC_BIT(1) 49 #define PBCQ_NEST_BAR_EN_PHB PPC_BIT(2) 50 #define PBCQ_NEST_BAR_EN_IRSN_RX PPC_BIT(3) 51 #define PBCQ_NEST_BAR_EN_IRSN_TX PPC_BIT(4) 52 53 #define PBCQ_PCI_REGS_COUNT 0x15 54 #define PBCQ_PCI_BAR2 0x0b 55 56 #define PBCQ_SPCI_REGS_COUNT 0x5 57 #define PBCQ_SPCI_ASB_ADDR 0x0 58 #define PBCQ_SPCI_ASB_STATUS 0x1 59 #define PBCQ_SPCI_ASB_DATA 0x2 60 #define PBCQ_SPCI_AIB_CAPP_EN 0x3 61 #define PBCQ_SPCI_CAPP_SEC_TMR 0x4 62 63 /* 64 * PHB MMIO registers 65 */ 66 67 /* PHB Fundamental register set A */ 68 #define PHB_LSI_SOURCE_ID 0x100 69 #define PHB_LSI_SRC_ID PPC_BITMASK(5, 12) 70 #define PHB_DMA_CHAN_STATUS 0x110 71 #define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27) 72 #define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28) 73 #define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29) 74 #define PHB_CPU_LOADSTORE_STATUS 0x120 75 #define PHB_CPU_LS_ANY_ERR PPC_BIT(27) 76 #define PHB_CPU_LS_ANY_ERR1 PPC_BIT(28) 77 #define PHB_CPU_LS_ANY_FREEZE PPC_BIT(29) 78 #define PHB_DMA_MSI_NODE_ID 0x128 79 #define PHB_DMAMSI_NID_FIXED PPC_BIT(0) 80 #define PHB_DMAMSI_NID PPC_BITMASK(24, 31) 81 #define PHB_CONFIG_DATA 0x130 82 #define PHB_LOCK0 0x138 83 #define PHB_CONFIG_ADDRESS 0x140 84 #define PHB_CA_ENABLE PPC_BIT(0) 85 #define PHB_CA_BUS PPC_BITMASK(4, 11) 86 #define PHB_CA_DEV PPC_BITMASK(12, 16) 87 #define PHB_CA_FUNC PPC_BITMASK(17, 19) 88 #define PHB_CA_REG PPC_BITMASK(20, 31) 89 #define PHB_CA_PE PPC_BITMASK(40, 47) 90 #define PHB_LOCK1 0x148 91 #define PHB_IVT_BAR 0x150 92 #define PHB_IVT_BAR_ENABLE PPC_BIT(0) 93 #define PHB_IVT_BASE_ADDRESS_MASK PPC_BITMASK(14, 48) 94 #define PHB_IVT_LENGTH_MASK PPC_BITMASK(52, 63) 95 #define PHB_RBA_BAR 0x158 96 #define PHB_RBA_BAR_ENABLE PPC_BIT(0) 97 #define PHB_RBA_BASE_ADDRESS PPC_BITMASK(14, 55) 98 #define PHB_PHB3_CONFIG 0x160 99 #define PHB_PHB3C_64B_TCE_EN PPC_BIT(2) 100 #define PHB_PHB3C_32BIT_MSI_EN PPC_BIT(8) 101 #define PHB_PHB3C_64BIT_MSI_EN PPC_BIT(14) 102 #define PHB_PHB3C_M32_EN PPC_BIT(16) 103 #define PHB_RTT_BAR 0x168 104 #define PHB_RTT_BAR_ENABLE PPC_BIT(0) 105 #define PHB_RTT_BASE_ADDRESS_MASK PPC_BITMASK(14, 46) 106 #define PHB_PELTV_BAR 0x188 107 #define PHB_PELTV_BAR_ENABLE PPC_BIT(0) 108 #define PHB_PELTV_BASE_ADDRESS PPC_BITMASK(14, 50) 109 #define PHB_M32_BASE_ADDR 0x190 110 #define PHB_M32_BASE_MASK 0x198 111 #define PHB_M32_START_ADDR 0x1a0 112 #define PHB_PEST_BAR 0x1a8 113 #define PHB_PEST_BAR_ENABLE PPC_BIT(0) 114 #define PHB_PEST_BASE_ADDRESS PPC_BITMASK(14, 51) 115 #define PHB_M64_UPPER_BITS 0x1f0 116 #define PHB_INTREP_TIMER 0x1f8 117 #define PHB_DMARD_SYNC 0x200 118 #define PHB_DMARD_SYNC_START PPC_BIT(0) 119 #define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1) 120 #define PHB_RTC_INVALIDATE 0x208 121 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0) 122 #define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16, 31) 123 #define PHB_TCE_KILL 0x210 124 #define PHB_TCE_KILL_ALL PPC_BIT(0) 125 #define PHB_TCE_SPEC_CTL 0x218 126 #define PHB_IODA_ADDR 0x220 127 #define PHB_IODA_AD_AUTOINC PPC_BIT(0) 128 #define PHB_IODA_AD_TSEL PPC_BITMASK(11, 15) 129 #define PHB_IODA_AD_TADR PPC_BITMASK(55, 63) 130 #define PHB_IODA_DATA0 0x228 131 #define PHB_FFI_REQUEST 0x238 132 #define PHB_FFI_LOCK_CLEAR PPC_BIT(3) 133 #define PHB_FFI_REQUEST_ISN PPC_BITMASK(49, 59) 134 #define PHB_FFI_LOCK 0x240 135 #define PHB_FFI_LOCK_STATE PPC_BIT(0) 136 #define PHB_XIVE_UPDATE 0x248 /* Broken in DD1 */ 137 #define PHB_PHB3_GEN_CAP 0x250 138 #define PHB_PHB3_TCE_CAP 0x258 139 #define PHB_PHB3_IRQ_CAP 0x260 140 #define PHB_PHB3_EEH_CAP 0x268 141 #define PHB_IVC_INVALIDATE 0x2a0 142 #define PHB_IVC_INVALIDATE_ALL PPC_BIT(0) 143 #define PHB_IVC_INVALIDATE_SID PPC_BITMASK(16, 31) 144 #define PHB_IVC_UPDATE 0x2a8 145 #define PHB_IVC_UPDATE_ENABLE_P PPC_BIT(0) 146 #define PHB_IVC_UPDATE_ENABLE_Q PPC_BIT(1) 147 #define PHB_IVC_UPDATE_ENABLE_SERVER PPC_BIT(2) 148 #define PHB_IVC_UPDATE_ENABLE_PRI PPC_BIT(3) 149 #define PHB_IVC_UPDATE_ENABLE_GEN PPC_BIT(4) 150 #define PHB_IVC_UPDATE_ENABLE_CON PPC_BIT(5) 151 #define PHB_IVC_UPDATE_GEN_MATCH PPC_BITMASK(6, 7) 152 #define PHB_IVC_UPDATE_SERVER PPC_BITMASK(8, 23) 153 #define PHB_IVC_UPDATE_PRI PPC_BITMASK(24, 31) 154 #define PHB_IVC_UPDATE_GEN PPC_BITMASK(32, 33) 155 #define PHB_IVC_UPDATE_P PPC_BITMASK(34, 34) 156 #define PHB_IVC_UPDATE_Q PPC_BITMASK(35, 35) 157 #define PHB_IVC_UPDATE_SID PPC_BITMASK(48, 63) 158 #define PHB_PAPR_ERR_INJ_CTL 0x2b0 159 #define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0) 160 #define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1) 161 #define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2) 162 #define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3) 163 #define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4) 164 #define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5) 165 #define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6) 166 #define PHB_PAPR_ERR_INJ_ADDR 0x2b8 167 #define PHB_PAPR_ERR_INJ_ADDR_MMIO PPC_BITMASK(16, 63) 168 #define PHB_PAPR_ERR_INJ_MASK 0x2c0 169 #define PHB_PAPR_ERR_INJ_MASK_CFG PPC_BITMASK(4, 11) 170 #define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16, 63) 171 #define PHB_ETU_ERR_SUMMARY 0x2c8 172 173 /* UTL registers */ 174 #define UTL_SYS_BUS_CONTROL 0x400 175 #define UTL_STATUS 0x408 176 #define UTL_SYS_BUS_AGENT_STATUS 0x410 177 #define UTL_SYS_BUS_AGENT_ERR_SEVERITY 0x418 178 #define UTL_SYS_BUS_AGENT_IRQ_EN 0x420 179 #define UTL_SYS_BUS_BURST_SZ_CONF 0x440 180 #define UTL_REVISION_ID 0x448 181 #define UTL_BCLK_DOMAIN_DBG1 0x460 182 #define UTL_BCLK_DOMAIN_DBG2 0x468 183 #define UTL_BCLK_DOMAIN_DBG3 0x470 184 #define UTL_BCLK_DOMAIN_DBG4 0x478 185 #define UTL_BCLK_DOMAIN_DBG5 0x480 186 #define UTL_BCLK_DOMAIN_DBG6 0x488 187 #define UTL_OUT_POST_HDR_BUF_ALLOC 0x4c0 188 #define UTL_OUT_POST_DAT_BUF_ALLOC 0x4d0 189 #define UTL_IN_POST_HDR_BUF_ALLOC 0x4e0 190 #define UTL_IN_POST_DAT_BUF_ALLOC 0x4f0 191 #define UTL_OUT_NP_BUF_ALLOC 0x500 192 #define UTL_IN_NP_BUF_ALLOC 0x510 193 #define UTL_PCIE_TAGS_ALLOC 0x520 194 #define UTL_GBIF_READ_TAGS_ALLOC 0x530 195 #define UTL_PCIE_PORT_CONTROL 0x540 196 #define UTL_PCIE_PORT_STATUS 0x548 197 #define UTL_PCIE_PORT_ERROR_SEV 0x550 198 #define UTL_PCIE_PORT_IRQ_EN 0x558 199 #define UTL_RC_STATUS 0x560 200 #define UTL_RC_ERR_SEVERITY 0x568 201 #define UTL_RC_IRQ_EN 0x570 202 #define UTL_EP_STATUS 0x578 203 #define UTL_EP_ERR_SEVERITY 0x580 204 #define UTL_EP_ERR_IRQ_EN 0x588 205 #define UTL_PCI_PM_CTRL1 0x590 206 #define UTL_PCI_PM_CTRL2 0x598 207 #define UTL_GP_CTL1 0x5a0 208 #define UTL_GP_CTL2 0x5a8 209 #define UTL_PCLK_DOMAIN_DBG1 0x5b0 210 #define UTL_PCLK_DOMAIN_DBG2 0x5b8 211 #define UTL_PCLK_DOMAIN_DBG3 0x5c0 212 #define UTL_PCLK_DOMAIN_DBG4 0x5c8 213 214 /* PCI-E Stack registers */ 215 #define PHB_PCIE_SYSTEM_CONFIG 0x600 216 #define PHB_PCIE_BUS_NUMBER 0x608 217 #define PHB_PCIE_SYSTEM_TEST 0x618 218 #define PHB_PCIE_LINK_MANAGEMENT 0x630 219 #define PHB_PCIE_LM_LINK_ACTIVE PPC_BIT(8) 220 #define PHB_PCIE_DLP_TRAIN_CTL 0x640 221 #define PHB_PCIE_DLP_TCTX_DISABLE PPC_BIT(1) 222 #define PHB_PCIE_DLP_TCRX_DISABLED PPC_BIT(16) 223 #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19) 224 #define PHB_PCIE_DLP_TC_DL_LINKUP PPC_BIT(21) 225 #define PHB_PCIE_DLP_TC_DL_PGRESET PPC_BIT(22) 226 #define PHB_PCIE_DLP_TC_DL_LINKACT PPC_BIT(23) 227 #define PHB_PCIE_SLOP_LOOPBACK_STATUS 0x648 228 #define PHB_PCIE_SYS_LINK_INIT 0x668 229 #define PHB_PCIE_UTL_CONFIG 0x670 230 #define PHB_PCIE_DLP_CONTROL 0x678 231 #define PHB_PCIE_UTL_ERRLOG1 0x680 232 #define PHB_PCIE_UTL_ERRLOG2 0x688 233 #define PHB_PCIE_UTL_ERRLOG3 0x690 234 #define PHB_PCIE_UTL_ERRLOG4 0x698 235 #define PHB_PCIE_DLP_ERRLOG1 0x6a0 236 #define PHB_PCIE_DLP_ERRLOG2 0x6a8 237 #define PHB_PCIE_DLP_ERR_STATUS 0x6b0 238 #define PHB_PCIE_DLP_ERR_COUNTERS 0x6b8 239 #define PHB_PCIE_UTL_ERR_INJECT 0x6c0 240 #define PHB_PCIE_TLDLP_ERR_INJECT 0x6c8 241 #define PHB_PCIE_LANE_EQ_CNTL0 0x6d0 242 #define PHB_PCIE_LANE_EQ_CNTL1 0x6d8 243 #define PHB_PCIE_LANE_EQ_CNTL2 0x6e0 244 #define PHB_PCIE_LANE_EQ_CNTL3 0x6e8 245 #define PHB_PCIE_STRAPPING 0x700 246 247 /* Fundamental register set B */ 248 #define PHB_VERSION 0x800 249 #define PHB_RESET 0x808 250 #define PHB_CONTROL 0x810 251 #define PHB_CTRL_IVE_128_BYTES PPC_BIT(24) 252 #define PHB_AIB_RX_CRED_INIT_TIMER 0x818 253 #define PHB_AIB_RX_CMD_CRED 0x820 254 #define PHB_AIB_RX_DATA_CRED 0x828 255 #define PHB_AIB_TX_CMD_CRED 0x830 256 #define PHB_AIB_TX_DATA_CRED 0x838 257 #define PHB_AIB_TX_CHAN_MAPPING 0x840 258 #define PHB_AIB_TAG_ENABLE 0x858 259 #define PHB_AIB_FENCE_CTRL 0x860 260 #define PHB_TCE_TAG_ENABLE 0x868 261 #define PHB_TCE_WATERMARK 0x870 262 #define PHB_TIMEOUT_CTRL1 0x878 263 #define PHB_TIMEOUT_CTRL2 0x880 264 #define PHB_Q_DMA_R 0x888 265 #define PHB_Q_DMA_R_QUIESCE_DMA PPC_BIT(0) 266 #define PHB_Q_DMA_R_AUTORESET PPC_BIT(1) 267 #define PHB_Q_DMA_R_DMA_RESP_STATUS PPC_BIT(4) 268 #define PHB_Q_DMA_R_MMIO_RESP_STATUS PPC_BIT(5) 269 #define PHB_Q_DMA_R_TCE_RESP_STATUS PPC_BIT(6) 270 #define PHB_AIB_TAG_STATUS 0x900 271 #define PHB_TCE_TAG_STATUS 0x908 272 273 /* FIR & Error registers */ 274 #define PHB_LEM_FIR_ACCUM 0xc00 275 #define PHB_LEM_FIR_AND_MASK 0xc08 276 #define PHB_LEM_FIR_OR_MASK 0xc10 277 #define PHB_LEM_ERROR_MASK 0xc18 278 #define PHB_LEM_ERROR_AND_MASK 0xc20 279 #define PHB_LEM_ERROR_OR_MASK 0xc28 280 #define PHB_LEM_ACTION0 0xc30 281 #define PHB_LEM_ACTION1 0xc38 282 #define PHB_LEM_WOF 0xc40 283 #define PHB_ERR_STATUS 0xc80 284 #define PHB_ERR1_STATUS 0xc88 285 #define PHB_ERR_INJECT 0xc90 286 #define PHB_ERR_LEM_ENABLE 0xc98 287 #define PHB_ERR_IRQ_ENABLE 0xca0 288 #define PHB_ERR_FREEZE_ENABLE 0xca8 289 #define PHB_ERR_AIB_FENCE_ENABLE 0xcb0 290 #define PHB_ERR_LOG_0 0xcc0 291 #define PHB_ERR_LOG_1 0xcc8 292 #define PHB_ERR_STATUS_MASK 0xcd0 293 #define PHB_ERR1_STATUS_MASK 0xcd8 294 295 #define PHB_OUT_ERR_STATUS 0xd00 296 #define PHB_OUT_ERR1_STATUS 0xd08 297 #define PHB_OUT_ERR_INJECT 0xd10 298 #define PHB_OUT_ERR_LEM_ENABLE 0xd18 299 #define PHB_OUT_ERR_IRQ_ENABLE 0xd20 300 #define PHB_OUT_ERR_FREEZE_ENABLE 0xd28 301 #define PHB_OUT_ERR_AIB_FENCE_ENABLE 0xd30 302 #define PHB_OUT_ERR_LOG_0 0xd40 303 #define PHB_OUT_ERR_LOG_1 0xd48 304 #define PHB_OUT_ERR_STATUS_MASK 0xd50 305 #define PHB_OUT_ERR1_STATUS_MASK 0xd58 306 307 #define PHB_INA_ERR_STATUS 0xd80 308 #define PHB_INA_ERR1_STATUS 0xd88 309 #define PHB_INA_ERR_INJECT 0xd90 310 #define PHB_INA_ERR_LEM_ENABLE 0xd98 311 #define PHB_INA_ERR_IRQ_ENABLE 0xda0 312 #define PHB_INA_ERR_FREEZE_ENABLE 0xda8 313 #define PHB_INA_ERR_AIB_FENCE_ENABLE 0xdb0 314 #define PHB_INA_ERR_LOG_0 0xdc0 315 #define PHB_INA_ERR_LOG_1 0xdc8 316 #define PHB_INA_ERR_STATUS_MASK 0xdd0 317 #define PHB_INA_ERR1_STATUS_MASK 0xdd8 318 319 #define PHB_INB_ERR_STATUS 0xe00 320 #define PHB_INB_ERR1_STATUS 0xe08 321 #define PHB_INB_ERR_INJECT 0xe10 322 #define PHB_INB_ERR_LEM_ENABLE 0xe18 323 #define PHB_INB_ERR_IRQ_ENABLE 0xe20 324 #define PHB_INB_ERR_FREEZE_ENABLE 0xe28 325 #define PHB_INB_ERR_AIB_FENCE_ENABLE 0xe30 326 #define PHB_INB_ERR_LOG_0 0xe40 327 #define PHB_INB_ERR_LOG_1 0xe48 328 #define PHB_INB_ERR_STATUS_MASK 0xe50 329 #define PHB_INB_ERR1_STATUS_MASK 0xe58 330 331 /* Performance monitor & Debug registers */ 332 #define PHB_TRACE_CONTROL 0xf80 333 #define PHB_PERFMON_CONFIG 0xf88 334 #define PHB_PERFMON_CTR0 0xf90 335 #define PHB_PERFMON_CTR1 0xf98 336 #define PHB_PERFMON_CTR2 0xfa0 337 #define PHB_PERFMON_CTR3 0xfa8 338 #define PHB_HOTPLUG_OVERRIDE 0xfb0 339 #define PHB_HPOVR_FORCE_RESAMPLE PPC_BIT(9) 340 #define PHB_HPOVR_PRESENCE_A PPC_BIT(10) 341 #define PHB_HPOVR_PRESENCE_B PPC_BIT(11) 342 #define PHB_HPOVR_LINK_ACTIVE PPC_BIT(12) 343 #define PHB_HPOVR_LINK_BIFURCATED PPC_BIT(13) 344 #define PHB_HPOVR_LINK_LANE_SWAPPED PPC_BIT(14) 345 346 /* 347 * IODA2 on-chip tables 348 */ 349 350 #define IODA2_TBL_LIST 1 351 #define IODA2_TBL_LXIVT 2 352 #define IODA2_TBL_IVC_CAM 3 353 #define IODA2_TBL_RBA 4 354 #define IODA2_TBL_RCAM 5 355 #define IODA2_TBL_MRT 6 356 #define IODA2_TBL_PESTA 7 357 #define IODA2_TBL_PESTB 8 358 #define IODA2_TBL_TVT 9 359 #define IODA2_TBL_TCAM 10 360 #define IODA2_TBL_TDR 11 361 #define IODA2_TBL_M64BT 16 362 #define IODA2_TBL_M32DT 17 363 #define IODA2_TBL_PEEV 20 364 365 /* LXIVT */ 366 #define IODA2_LXIVT_SERVER PPC_BITMASK(8, 23) 367 #define IODA2_LXIVT_PRIORITY PPC_BITMASK(24, 31) 368 #define IODA2_LXIVT_NODE_ID PPC_BITMASK(56, 63) 369 370 /* IVT */ 371 #define IODA2_IVT_SERVER PPC_BITMASK(0, 23) 372 #define IODA2_IVT_PRIORITY PPC_BITMASK(24, 31) 373 #define IODA2_IVT_GEN PPC_BITMASK(37, 38) 374 #define IODA2_IVT_P PPC_BITMASK(39, 39) 375 #define IODA2_IVT_Q PPC_BITMASK(47, 47) 376 #define IODA2_IVT_PE PPC_BITMASK(48, 63) 377 378 /* TVT */ 379 #define IODA2_TVT_TABLE_ADDR PPC_BITMASK(0, 47) 380 #define IODA2_TVT_NUM_LEVELS PPC_BITMASK(48, 50) 381 #define IODA2_TVE_1_LEVEL 0 382 #define IODA2_TVE_2_LEVELS 1 383 #define IODA2_TVE_3_LEVELS 2 384 #define IODA2_TVE_4_LEVELS 3 385 #define IODA2_TVE_5_LEVELS 4 386 #define IODA2_TVT_TCE_TABLE_SIZE PPC_BITMASK(51, 55) 387 #define IODA2_TVT_IO_PSIZE PPC_BITMASK(59, 63) 388 389 /* PESTA */ 390 #define IODA2_PESTA_MMIO_FROZEN PPC_BIT(0) 391 392 /* PESTB */ 393 #define IODA2_PESTB_DMA_STOPPED PPC_BIT(0) 394 395 /* M32DT */ 396 #define IODA2_M32DT_PE PPC_BITMASK(8, 15) 397 398 /* M64BT */ 399 #define IODA2_M64BT_ENABLE PPC_BIT(0) 400 #define IODA2_M64BT_SINGLE_PE PPC_BIT(1) 401 #define IODA2_M64BT_BASE PPC_BITMASK(2, 31) 402 #define IODA2_M64BT_MASK PPC_BITMASK(34, 63) 403 #define IODA2_M64BT_SINGLE_BASE PPC_BITMASK(2, 26) 404 #define IODA2_M64BT_PE_HI PPC_BITMASK(27, 31) 405 #define IODA2_M64BT_SINGLE_MASK PPC_BITMASK(34, 58) 406 #define IODA2_M64BT_PE_LOW PPC_BITMASK(59, 63) 407 408 /* 409 * IODA2 in-memory tables 410 */ 411 412 /* 413 * PEST 414 * 415 * 2x8 bytes entries, PEST0 and PEST1 416 */ 417 418 #define IODA2_PEST0_MMIO_CAUSE PPC_BIT(2) 419 #define IODA2_PEST0_CFG_READ PPC_BIT(3) 420 #define IODA2_PEST0_CFG_WRITE PPC_BIT(4) 421 #define IODA2_PEST0_TTYPE PPC_BITMASK(5, 7) 422 #define PEST_TTYPE_DMA_WRITE 0 423 #define PEST_TTYPE_MSI 1 424 #define PEST_TTYPE_DMA_READ 2 425 #define PEST_TTYPE_DMA_READ_RESP 3 426 #define PEST_TTYPE_MMIO_LOAD 4 427 #define PEST_TTYPE_MMIO_STORE 5 428 #define PEST_TTYPE_OTHER 7 429 #define IODA2_PEST0_CA_RETURN PPC_BIT(8) 430 #define IODA2_PEST0_UTL_RTOS_TIMEOUT PPC_BIT(8) /* Same bit as CA return */ 431 #define IODA2_PEST0_UR_RETURN PPC_BIT(9) 432 #define IODA2_PEST0_UTL_NONFATAL PPC_BIT(10) 433 #define IODA2_PEST0_UTL_FATAL PPC_BIT(11) 434 #define IODA2_PEST0_PARITY_UE PPC_BIT(13) 435 #define IODA2_PEST0_UTL_CORRECTABLE PPC_BIT(14) 436 #define IODA2_PEST0_UTL_INTERRUPT PPC_BIT(15) 437 #define IODA2_PEST0_MMIO_XLATE PPC_BIT(16) 438 #define IODA2_PEST0_IODA2_ERROR PPC_BIT(16) /* Same bit as MMIO xlate */ 439 #define IODA2_PEST0_TCE_PAGE_FAULT PPC_BIT(18) 440 #define IODA2_PEST0_TCE_ACCESS_FAULT PPC_BIT(19) 441 #define IODA2_PEST0_DMA_RESP_TIMEOUT PPC_BIT(20) 442 #define IODA2_PEST0_AIB_SIZE_INVALID PPC_BIT(21) 443 #define IODA2_PEST0_LEM_BIT PPC_BITMASK(26, 31) 444 #define IODA2_PEST0_RID PPC_BITMASK(32, 47) 445 #define IODA2_PEST0_MSI_DATA PPC_BITMASK(48, 63) 446 447 #define IODA2_PEST1_FAIL_ADDR PPC_BITMASK(3, 63) 448 449 450 #endif /* PCI_HOST_PNV_PHB3_REGS_H */ 451