1 /* 2 * QEMU PowerPC PowerNV (POWER9) PHB4 model 3 * 4 * Copyright (c) 2018-2020, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PCI_HOST_PNV_PHB4_H 11 #define PCI_HOST_PNV_PHB4_H 12 13 #include "hw/pci/pci_bus.h" 14 #include "hw/ppc/xive.h" 15 #include "qom/object.h" 16 17 typedef struct PnvPhb4PecState PnvPhb4PecState; 18 typedef struct PnvPhb4PecStack PnvPhb4PecStack; 19 typedef struct PnvPHB4 PnvPHB4; 20 typedef struct PnvPHB PnvPHB; 21 typedef struct PnvChip PnvChip; 22 23 /* 24 * We have one such address space wrapper per possible device under 25 * the PHB since they need to be assigned statically at qemu device 26 * creation time. The relationship to a PE is done later 27 * dynamically. This means we can potentially create a lot of these 28 * guys. Q35 stores them as some kind of radix tree but we never 29 * really need to do fast lookups so instead we simply keep a QLIST of 30 * them for now, we can add the radix if needed later on. 31 * 32 * We do cache the PE number to speed things up a bit though. 33 */ 34 typedef struct PnvPhb4DMASpace { 35 PCIBus *bus; 36 uint8_t devfn; 37 int pe_num; /* Cached PE number */ 38 #define PHB_INVALID_PE (-1) 39 PnvPHB4 *phb; 40 AddressSpace dma_as; 41 IOMMUMemoryRegion dma_mr; 42 MemoryRegion msi32_mr; 43 MemoryRegion msi64_mr; 44 QLIST_ENTRY(PnvPhb4DMASpace) list; 45 } PnvPhb4DMASpace; 46 47 /* 48 * PHB4 PCIe Root Bus 49 */ 50 #define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root" 51 struct PnvPHB4RootBus { 52 PCIBus parent; 53 54 uint32_t chip_id; 55 uint32_t phb_id; 56 }; 57 OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4RootBus, PNV_PHB4_ROOT_BUS) 58 59 /* 60 * PHB4 PCIe Host Bridge for PowerNV machines (POWER9) 61 */ 62 #define TYPE_PNV_PHB4 "pnv-phb4" 63 OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) 64 65 #define PNV_PHB4_MAX_LSIs 8 66 #define PNV_PHB4_MAX_INTs 4096 67 #define PNV_PHB4_MAX_MIST (PNV_PHB4_MAX_INTs >> 2) 68 #define PNV_PHB4_MAX_MMIO_WINDOWS 32 69 #define PNV_PHB4_MIN_MMIO_WINDOWS 16 70 #define PNV_PHB4_NUM_REGS (0x3000 >> 3) 71 #define PNV_PHB4_MAX_PEs 512 72 #define PNV_PHB4_MAX_TVEs (PNV_PHB4_MAX_PEs * 2) 73 #define PNV_PHB4_MAX_PEEVs (PNV_PHB4_MAX_PEs / 64) 74 #define PNV_PHB4_MAX_MBEs (PNV_PHB4_MAX_MMIO_WINDOWS * 2) 75 76 #define PNV_PHB4_VERSION 0x000000a400000002ull 77 #define PNV_PHB4_DEVICE_ID 0x04c1 78 79 #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) 80 81 struct PnvPHB4 { 82 DeviceState parent; 83 84 PnvPHB *phb_base; 85 86 uint32_t chip_id; 87 uint32_t phb_id; 88 89 /* The owner PEC */ 90 PnvPhb4PecState *pec; 91 92 char bus_path[8]; 93 94 /* Main register images */ 95 uint64_t regs[PNV_PHB4_NUM_REGS]; 96 MemoryRegion mr_regs; 97 98 /* Extra SCOM-only register */ 99 uint64_t scom_hv_ind_addr_reg; 100 101 /* 102 * Geometry of the PHB. There are two types, small and big PHBs, a 103 * number of resources (number of PEs, windows etc...) are doubled 104 * for a big PHB 105 */ 106 bool big_phb; 107 108 /* Memory regions for MMIO space */ 109 MemoryRegion mr_mmio[PNV_PHB4_MAX_MMIO_WINDOWS]; 110 111 /* PCI side space */ 112 MemoryRegion pci_mmio; 113 MemoryRegion pci_io; 114 115 /* PCI registers (excluding pass-through) */ 116 #define PHB4_PEC_PCI_STK_REGS_COUNT 0xf 117 uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT]; 118 MemoryRegion pci_regs_mr; 119 120 /* Nest registers */ 121 #define PHB4_PEC_NEST_STK_REGS_COUNT 0x17 122 uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT]; 123 MemoryRegion nest_regs_mr; 124 125 /* PHB pass-through XSCOM */ 126 MemoryRegion phb_regs_mr; 127 128 /* Memory windows from PowerBus to PHB */ 129 MemoryRegion phbbar; 130 MemoryRegion intbar; 131 MemoryRegion mmbar0; 132 MemoryRegion mmbar1; 133 uint64_t mmio0_base; 134 uint64_t mmio0_size; 135 uint64_t mmio1_base; 136 uint64_t mmio1_size; 137 138 /* On-chip IODA tables */ 139 uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs]; 140 uint64_t ioda_MIST[PNV_PHB4_MAX_MIST]; 141 uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs]; 142 uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs]; 143 uint64_t ioda_MDT[PNV_PHB4_MAX_PEs]; 144 uint64_t ioda_PEEV[PNV_PHB4_MAX_PEEVs]; 145 146 /* 147 * The internal PESTA/B is 2 bits per PE split into two tables, we 148 * store them in a single array here to avoid wasting space. 149 */ 150 uint8_t ioda_PEST_AB[PNV_PHB4_MAX_PEs]; 151 152 /* P9 Interrupt generation */ 153 XiveSource xsrc; 154 qemu_irq *qirqs; 155 156 QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces; 157 }; 158 159 void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon); 160 int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index); 161 void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb); 162 extern const MemoryRegionOps pnv_phb4_xscom_ops; 163 164 /* 165 * PHB4 PEC (PCI Express Controller) 166 */ 167 #define TYPE_PNV_PHB4_PEC "pnv-phb4-pec" 168 OBJECT_DECLARE_TYPE(PnvPhb4PecState, PnvPhb4PecClass, PNV_PHB4_PEC) 169 170 struct PnvPhb4PecState { 171 DeviceState parent; 172 173 /* PEC number in chip */ 174 uint32_t index; 175 uint32_t chip_id; 176 177 MemoryRegion *system_memory; 178 179 /* Nest registers, excuding per-stack */ 180 #define PHB4_PEC_NEST_REGS_COUNT 0xf 181 uint64_t nest_regs[PHB4_PEC_NEST_REGS_COUNT]; 182 MemoryRegion nest_regs_mr; 183 184 /* PCI registers, excluding per-stack */ 185 #define PHB4_PEC_PCI_REGS_COUNT 0x3 186 uint64_t pci_regs[PHB4_PEC_PCI_REGS_COUNT]; 187 MemoryRegion pci_regs_mr; 188 189 /* PHBs */ 190 uint32_t num_phbs; 191 192 PnvChip *chip; 193 }; 194 195 196 struct PnvPhb4PecClass { 197 DeviceClass parent_class; 198 199 uint32_t (*xscom_nest_base)(PnvPhb4PecState *pec); 200 uint32_t xscom_nest_size; 201 uint32_t (*xscom_pci_base)(PnvPhb4PecState *pec); 202 uint32_t xscom_pci_size; 203 const char *compat; 204 int compat_size; 205 const char *stk_compat; 206 int stk_compat_size; 207 uint64_t version; 208 const char *phb_type; 209 const uint32_t *num_phbs; 210 }; 211 212 /* 213 * POWER10 definitions 214 */ 215 216 #define TYPE_PNV_PHB5 "pnv-phb5" 217 #define PNV_PHB5(obj) \ 218 OBJECT_CHECK(PnvPhb4, (obj), TYPE_PNV_PHB5) 219 220 #define PNV_PHB5_VERSION 0x000000a500000001ull 221 #define PNV_PHB5_DEVICE_ID 0x0652 222 223 #define TYPE_PNV_PHB5_PEC "pnv-phb5-pec" 224 #define PNV_PHB5_PEC(obj) \ 225 OBJECT_CHECK(PnvPhb4PecState, (obj), TYPE_PNV_PHB5_PEC) 226 227 #endif /* PCI_HOST_PNV_PHB4_H */ 228