10d09e41aSPaolo Bonzini /* 20d09e41aSPaolo Bonzini * q35.h 30d09e41aSPaolo Bonzini * 40d09e41aSPaolo Bonzini * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> 50d09e41aSPaolo Bonzini * VA Linux Systems Japan K.K. 60d09e41aSPaolo Bonzini * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 70d09e41aSPaolo Bonzini * 80d09e41aSPaolo Bonzini * This program is free software; you can redistribute it and/or modify 90d09e41aSPaolo Bonzini * it under the terms of the GNU General Public License as published by 100d09e41aSPaolo Bonzini * the Free Software Foundation; either version 2 of the License, or 110d09e41aSPaolo Bonzini * (at your option) any later version. 120d09e41aSPaolo Bonzini * 130d09e41aSPaolo Bonzini * This program is distributed in the hope that it will be useful, 140d09e41aSPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of 150d09e41aSPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 160d09e41aSPaolo Bonzini * GNU General Public License for more details. 170d09e41aSPaolo Bonzini * 18e361a772SThomas Huth * You should have received a copy of the GNU General Public License 19e361a772SThomas Huth * along with this program; if not, see <http://www.gnu.org/licenses/> 200d09e41aSPaolo Bonzini */ 210d09e41aSPaolo Bonzini 220d09e41aSPaolo Bonzini #ifndef HW_Q35_H 230d09e41aSPaolo Bonzini #define HW_Q35_H 240d09e41aSPaolo Bonzini 25edf5ca5dSMarkus Armbruster #include "hw/pci/pci_device.h" 260d09e41aSPaolo Bonzini #include "hw/pci/pcie_host.h" 270d09e41aSPaolo Bonzini #include "hw/pci-host/pam.h" 28f404220eSIgor Mammedov #include "qemu/units.h" 29577aa489SPhilippe Mathieu-Daudé #include "qemu/range.h" 30db1015e9SEduardo Habkost #include "qom/object.h" 310d09e41aSPaolo Bonzini 320d09e41aSPaolo Bonzini #define TYPE_Q35_HOST_DEVICE "q35-pcihost" 338063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(Q35PCIHost, Q35_HOST_DEVICE) 340d09e41aSPaolo Bonzini 350d09e41aSPaolo Bonzini #define TYPE_MCH_PCI_DEVICE "mch" 368063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(MCHPCIState, MCH_PCI_DEVICE) 370d09e41aSPaolo Bonzini 38db1015e9SEduardo Habkost struct MCHPCIState { 39ce88812fSHu Tao /*< private >*/ 40ce88812fSHu Tao PCIDevice parent_obj; 41ce88812fSHu Tao /*< public >*/ 42ce88812fSHu Tao 430d09e41aSPaolo Bonzini MemoryRegion *ram_memory; 440d09e41aSPaolo Bonzini MemoryRegion *pci_address_space; 450d09e41aSPaolo Bonzini MemoryRegion *system_memory; 460d09e41aSPaolo Bonzini MemoryRegion *address_space_io; 47f6a3c86eSPhilippe Mathieu-Daudé PAMMemoryRegion pam_regions[PAM_REGIONS_COUNT]; 4864130fa4SPaolo Bonzini MemoryRegion smram_region, open_high_smram; 4964130fa4SPaolo Bonzini MemoryRegion smram, low_smram, high_smram; 50bafc90bdSGerd Hoffmann MemoryRegion tseg_blackhole, tseg_window; 51f404220eSIgor Mammedov MemoryRegion smbase_blackhole, smbase_window; 52f404220eSIgor Mammedov bool has_smram_at_smbase; 53b07bf7b7SIsaku Yamahata bool has_smm_ranges; 5401c9742dSMarkus Armbruster Range pci_hole; 55401f2f3eSEfimov Vasily uint64_t below_4g_mem_size; 56401f2f3eSEfimov Vasily uint64_t above_4g_mem_size; 5739848901SIgor Mammedov uint64_t pci_hole64_size; 582f295167SLaszlo Ersek uint16_t ext_tseg_mbytes; 59db1015e9SEduardo Habkost }; 600d09e41aSPaolo Bonzini 61db1015e9SEduardo Habkost struct Q35PCIHost { 62ce88812fSHu Tao /*< private >*/ 63ce88812fSHu Tao PCIExpressHost parent_obj; 64ce88812fSHu Tao /*< public >*/ 65ce88812fSHu Tao 669fa99d25SMarcel Apfelbaum bool pci_hole64_fix; 670d09e41aSPaolo Bonzini MCHPCIState mch; 68db1015e9SEduardo Habkost }; 690d09e41aSPaolo Bonzini 700d09e41aSPaolo Bonzini #define Q35_MASK(bit, ms_bit, ls_bit) \ 710d09e41aSPaolo Bonzini ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) 720d09e41aSPaolo Bonzini 730d09e41aSPaolo Bonzini /* 740d09e41aSPaolo Bonzini * gmch part 750d09e41aSPaolo Bonzini */ 760d09e41aSPaolo Bonzini 770d09e41aSPaolo Bonzini /* PCI configuration */ 780d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE "MCH" 790d09e41aSPaolo Bonzini 800d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8 810d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_CONFIG_DATA 0xcfc 820d09e41aSPaolo Bonzini 830d09e41aSPaolo Bonzini /* D0:F0 configuration space */ 84451f7846SRichard W.M. Jones #define MCH_HOST_BRIDGE_REVISION_DEFAULT 0x0 850d09e41aSPaolo Bonzini 862f295167SLaszlo Ersek #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES 0x50 872f295167SLaszlo Ersek #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE 2 882f295167SLaszlo Ersek #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff 892f295167SLaszlo Ersek #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff 902f295167SLaszlo Ersek 91f404220eSIgor Mammedov #define MCH_HOST_BRIDGE_SMBASE_SIZE (128 * KiB) 92f404220eSIgor Mammedov #define MCH_HOST_BRIDGE_SMBASE_ADDR 0x30000 93f404220eSIgor Mammedov #define MCH_HOST_BRIDGE_F_SMBASE 0x9c 94f404220eSIgor Mammedov #define MCH_HOST_BRIDGE_F_SMBASE_QUERY 0xff 95f404220eSIgor Mammedov #define MCH_HOST_BRIDGE_F_SMBASE_IN_RAM 0x01 96f404220eSIgor Mammedov #define MCH_HOST_BRIDGE_F_SMBASE_LCK 0x02 97f404220eSIgor Mammedov 980d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */ 990d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */ 1000d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000 1013459a625SMichael S. Tsirkin #define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000) /* 256M */ 1020d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 28) 1030d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26)) 1040d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25)) 1050d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1)) 1060d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1)) 1070d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1)) 1080d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1)) 1090d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1)) 1100d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1) 1110d09e41aSPaolo Bonzini 1120d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_NB 7 1130d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_SIZE 7 1140d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM0 0x90 1150d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000 1160d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000 /* 16KB */ 1170d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM1 0x91 1180d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000 1190d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000 1200d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM2 0x92 1210d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM3 0x93 1220d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM4 0x94 1230d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000 1240d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000 1250d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM5 0x95 1260d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM6 0x96 1270d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4)) 1280d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4)) 1290d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4)) 1300d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2) 1310d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1) 1320d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3) 1330d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2) 1340d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1) 1350d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3) 1360d09e41aSPaolo Bonzini 137263cf436SBALATON Zoltan #define MCH_HOST_BRIDGE_SMRAM 0x9d 13864130fa4SPaolo Bonzini #define MCH_HOST_BRIDGE_SMRAM_SIZE 2 1390d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6)) 1400d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5)) 1410d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4)) 1420d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3)) 1430d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7) 1440d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */ 1450d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000 1460d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_SMRAM_C_END 0xc0000 1470d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000 1480d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000 14977447524SGerd Hoffmann #define MCH_HOST_BRIDGE_SMRAM_DEFAULT \ 15077447524SGerd Hoffmann MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG 151b66a67d7SGerd Hoffmann #define MCH_HOST_BRIDGE_SMRAM_WMASK \ 152b66a67d7SGerd Hoffmann (MCH_HOST_BRIDGE_SMRAM_D_OPEN | \ 153b66a67d7SGerd Hoffmann MCH_HOST_BRIDGE_SMRAM_D_CLS | \ 154b66a67d7SGerd Hoffmann MCH_HOST_BRIDGE_SMRAM_D_LCK | \ 155b66a67d7SGerd Hoffmann MCH_HOST_BRIDGE_SMRAM_G_SMRAME) 15668c77acfSGerd Hoffmann #define MCH_HOST_BRIDGE_SMRAM_WMASK_LCK \ 15768c77acfSGerd Hoffmann MCH_HOST_BRIDGE_SMRAM_D_CLS 1580d09e41aSPaolo Bonzini 1590d09e41aSPaolo Bonzini #define MCH_HOST_BRIDGE_ESMRAMC 0x9e 16064130fa4SPaolo Bonzini #define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7)) 16164130fa4SPaolo Bonzini #define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 6)) 16264130fa4SPaolo Bonzini #define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 5)) 16364130fa4SPaolo Bonzini #define MCH_HOST_BRIDGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 4)) 16464130fa4SPaolo Bonzini #define MCH_HOST_BRIDGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 3)) 165263cf436SBALATON Zoltan #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1)) 166263cf436SBALATON Zoltan #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1)) 167263cf436SBALATON Zoltan #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1)) 168263cf436SBALATON Zoltan #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1)) 169263cf436SBALATON Zoltan #define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1) 17077447524SGerd Hoffmann #define MCH_HOST_BRIDGE_ESMRAMC_DEFAULT \ 17177447524SGerd Hoffmann (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \ 17277447524SGerd Hoffmann MCH_HOST_BRIDGE_ESMRAMC_SM_L1 | \ 17377447524SGerd Hoffmann MCH_HOST_BRIDGE_ESMRAMC_SM_L2) 174b66a67d7SGerd Hoffmann #define MCH_HOST_BRIDGE_ESMRAMC_WMASK \ 175b66a67d7SGerd Hoffmann (MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME | \ 176b66a67d7SGerd Hoffmann MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK | \ 177b66a67d7SGerd Hoffmann MCH_HOST_BRIDGE_ESMRAMC_T_EN) 17868c77acfSGerd Hoffmann #define MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK 0 1790d09e41aSPaolo Bonzini 1800d09e41aSPaolo Bonzini /* D1:F0 PCIE* port*/ 1810d09e41aSPaolo Bonzini #define MCH_PCIE_DEV 1 1820d09e41aSPaolo Bonzini #define MCH_PCIE_FUNC 0 1830d09e41aSPaolo Bonzini 1846f1426abSMichael S. Tsirkin uint64_t mch_mcfg_base(void); 1856f1426abSMichael S. Tsirkin 186cfc13df4SPeter Xu /* 1875bb8590dSStefan Weil * Arbitrary but unique BNF number for IOAPIC device. 188cfc13df4SPeter Xu * 189cfc13df4SPeter Xu * TODO: make sure there would have no conflict with real PCI bus 190cfc13df4SPeter Xu */ 191cfc13df4SPeter Xu #define Q35_PSEUDO_BUS_PLATFORM (0xff) 192cfc13df4SPeter Xu #define Q35_PSEUDO_DEVFN_IOAPIC (0x00) 193cfc13df4SPeter Xu 1940d09e41aSPaolo Bonzini #endif /* HW_Q35_H */ 195