1 /* 2 * QEMU SPAPR PCI BUS definitions 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PCI_HOST_SPAPR_H 21 #define PCI_HOST_SPAPR_H 22 23 #include "hw/ppc/spapr.h" 24 #include "hw/pci/pci.h" 25 #include "hw/pci/pci_host.h" 26 #include "hw/ppc/xics.h" 27 28 #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge" 29 30 #define SPAPR_PCI_HOST_BRIDGE(obj) \ 31 OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE) 32 33 #define SPAPR_PCI_DMA_MAX_WINDOWS 2 34 35 typedef struct sPAPRPHBState sPAPRPHBState; 36 37 typedef struct spapr_pci_msi { 38 uint32_t first_irq; 39 uint32_t num; 40 } spapr_pci_msi; 41 42 typedef struct spapr_pci_msi_mig { 43 uint32_t key; 44 spapr_pci_msi value; 45 } spapr_pci_msi_mig; 46 47 struct sPAPRPHBState { 48 PCIHostState parent_obj; 49 50 uint32_t index; 51 uint64_t buid; 52 char *dtbusname; 53 bool dr_enabled; 54 55 MemoryRegion memspace, iospace; 56 hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size; 57 uint64_t mem64_win_pciaddr; 58 hwaddr io_win_addr, io_win_size; 59 MemoryRegion mem32window, mem64window, iowindow, msiwindow; 60 61 uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS]; 62 hwaddr dma_win_addr, dma_win_size; 63 AddressSpace iommu_as; 64 MemoryRegion iommu_root; 65 66 struct spapr_pci_lsi { 67 uint32_t irq; 68 } lsi_table[PCI_NUM_PINS]; 69 70 GHashTable *msi; 71 /* Temporary cache for migration purposes */ 72 int32_t msi_devs_num; 73 spapr_pci_msi_mig *msi_devs; 74 75 QLIST_ENTRY(sPAPRPHBState) list; 76 77 bool ddw_enabled; 78 uint64_t page_size_mask; 79 uint64_t dma64_win_addr; 80 81 uint32_t numa_node; 82 }; 83 84 #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL 85 #define SPAPR_PCI_MEM32_WIN_SIZE \ 86 ((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET) 87 #define SPAPR_PCI_MEM64_WIN_SIZE 0x10000000000ULL /* 1 TiB */ 88 89 /* Without manual configuration, all PCI outbound windows will be 90 * within this range */ 91 #define SPAPR_PCI_BASE (1ULL << 45) /* 32 TiB */ 92 #define SPAPR_PCI_LIMIT (1ULL << 46) /* 64 TiB */ 93 94 #define SPAPR_PCI_2_7_MMIO_WIN_SIZE 0xf80000000 95 #define SPAPR_PCI_IO_WIN_SIZE 0x10000 96 97 #define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL 98 99 static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin) 100 { 101 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 102 103 return xics_get_qirq(spapr->xics, phb->lsi_table[pin].irq); 104 } 105 106 PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index); 107 108 int spapr_populate_pci_dt(sPAPRPHBState *phb, 109 uint32_t xics_phandle, 110 void *fdt); 111 112 void spapr_pci_rtas_init(void); 113 114 sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid); 115 PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, 116 uint32_t config_addr); 117 118 /* VFIO EEH hooks */ 119 #ifdef CONFIG_LINUX 120 bool spapr_phb_eeh_available(sPAPRPHBState *sphb); 121 int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb, 122 unsigned int addr, int option); 123 int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state); 124 int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option); 125 int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb); 126 void spapr_phb_vfio_reset(DeviceState *qdev); 127 #else 128 static inline bool spapr_phb_eeh_available(sPAPRPHBState *sphb) 129 { 130 return false; 131 } 132 static inline int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb, 133 unsigned int addr, int option) 134 { 135 return RTAS_OUT_HW_ERROR; 136 } 137 static inline int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, 138 int *state) 139 { 140 return RTAS_OUT_HW_ERROR; 141 } 142 static inline int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option) 143 { 144 return RTAS_OUT_HW_ERROR; 145 } 146 static inline int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb) 147 { 148 return RTAS_OUT_HW_ERROR; 149 } 150 static inline void spapr_phb_vfio_reset(DeviceState *qdev) 151 { 152 } 153 #endif 154 155 void spapr_phb_dma_reset(sPAPRPHBState *sphb); 156 157 #endif /* PCI_HOST_SPAPR_H */ 158