1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "exec/memory.h" 5 #include "sysemu/dma.h" 6 7 /* PCI includes legacy ISA access. */ 8 #include "hw/isa/isa.h" 9 10 extern bool pci_available; 11 12 /* PCI bus */ 13 14 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 15 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 16 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 17 #define PCI_FUNC(devfn) ((devfn) & 0x07) 18 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 19 #define PCI_BDF_TO_DEVFN(x) ((x) & 0xff) 20 #define PCI_BUS_MAX 256 21 #define PCI_DEVFN_MAX 256 22 #define PCI_SLOT_MAX 32 23 #define PCI_FUNC_MAX 8 24 25 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 26 #include "hw/pci/pci_ids.h" 27 28 /* QEMU-specific Vendor and Device ID definitions */ 29 30 /* IBM (0x1014) */ 31 #define PCI_DEVICE_ID_IBM_440GX 0x027f 32 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 33 34 /* Hitachi (0x1054) */ 35 #define PCI_VENDOR_ID_HITACHI 0x1054 36 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 37 38 /* Apple (0x106b) */ 39 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 40 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 41 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 42 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 43 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 44 45 /* Realtek (0x10ec) */ 46 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 47 48 /* Xilinx (0x10ee) */ 49 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 50 51 /* Marvell (0x11ab) */ 52 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 53 54 /* QEMU/Bochs VGA (0x1234) */ 55 #define PCI_VENDOR_ID_QEMU 0x1234 56 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 57 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 58 59 /* VMWare (0x15ad) */ 60 #define PCI_VENDOR_ID_VMWARE 0x15ad 61 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 62 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 63 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 64 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 65 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 66 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 67 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 68 69 /* Intel (0x8086) */ 70 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 71 #define PCI_DEVICE_ID_INTEL_82557 0x1229 72 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 73 74 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 75 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 76 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 77 #define PCI_SUBDEVICE_ID_QEMU 0x1100 78 79 /* legacy virtio-pci devices */ 80 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 81 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 82 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 84 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 85 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 86 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 87 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 88 89 /* 90 * modern virtio-pci devices get their id assigned automatically, 91 * there is no need to add #defines here. It gets calculated as 92 * 93 * PCI_DEVICE_ID = PCI_DEVICE_ID_VIRTIO_10_BASE + 94 * virtio_bus_get_vdev_id(bus) 95 */ 96 #define PCI_DEVICE_ID_VIRTIO_10_BASE 0x1040 97 98 #define PCI_VENDOR_ID_REDHAT 0x1b36 99 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 100 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 101 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 102 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 103 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 104 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 105 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 106 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 107 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 108 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 109 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 110 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 111 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 112 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e 113 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f 114 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 115 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 116 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012 117 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 118 119 #define FMT_PCIBUS PRIx64 120 121 typedef uint64_t pcibus_t; 122 123 struct PCIHostDeviceAddress { 124 unsigned int domain; 125 unsigned int bus; 126 unsigned int slot; 127 unsigned int function; 128 }; 129 130 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 131 uint32_t address, uint32_t data, int len); 132 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 133 uint32_t address, int len); 134 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 135 pcibus_t addr, pcibus_t size, int type); 136 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 137 138 typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg); 139 typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector); 140 typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector); 141 142 typedef struct PCIIORegion { 143 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 144 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 145 pcibus_t size; 146 uint8_t type; 147 MemoryRegion *memory; 148 MemoryRegion *address_space; 149 } PCIIORegion; 150 151 #define PCI_ROM_SLOT 6 152 #define PCI_NUM_REGIONS 7 153 154 enum { 155 QEMU_PCI_VGA_MEM, 156 QEMU_PCI_VGA_IO_LO, 157 QEMU_PCI_VGA_IO_HI, 158 QEMU_PCI_VGA_NUM_REGIONS, 159 }; 160 161 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 162 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 163 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 164 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 165 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 166 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 167 168 #include "hw/pci/pci_regs.h" 169 #include "hw/pci/pcie.h" 170 171 /* PCI HEADER_TYPE */ 172 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 173 174 /* Size of the standard PCI config header */ 175 #define PCI_CONFIG_HEADER_SIZE 0x40 176 /* Size of the standard PCI config space */ 177 #define PCI_CONFIG_SPACE_SIZE 0x100 178 /* Size of the standard PCIe config space: 4KB */ 179 #define PCIE_CONFIG_SPACE_SIZE 0x1000 180 181 #define PCI_NUM_PINS 4 /* A-D */ 182 183 /* Bits in cap_present field. */ 184 enum { 185 QEMU_PCI_CAP_MSI = 0x1, 186 QEMU_PCI_CAP_MSIX = 0x2, 187 QEMU_PCI_CAP_EXPRESS = 0x4, 188 189 /* multifunction capable device */ 190 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 191 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 192 193 /* command register SERR bit enabled - unused since QEMU v5.0 */ 194 #define QEMU_PCI_CAP_SERR_BITNR 4 195 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 196 /* Standard hot plug controller. */ 197 #define QEMU_PCI_SHPC_BITNR 5 198 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 199 #define QEMU_PCI_SLOTID_BITNR 6 200 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 201 /* PCI Express capability - Power Controller Present */ 202 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 203 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 204 /* Link active status in endpoint capability is always set */ 205 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 206 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 207 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 208 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), 209 #define QEMU_PCIE_CXL_BITNR 10 210 QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR), 211 }; 212 213 #define TYPE_PCI_DEVICE "pci-device" 214 typedef struct PCIDeviceClass PCIDeviceClass; 215 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass, 216 PCI_DEVICE, TYPE_PCI_DEVICE) 217 218 /* 219 * Implemented by devices that can be plugged on CXL buses. In the spec, this is 220 * actually a "CXL Component, but we name it device to match the PCI naming. 221 */ 222 #define INTERFACE_CXL_DEVICE "cxl-device" 223 224 /* Implemented by devices that can be plugged on PCI Express buses */ 225 #define INTERFACE_PCIE_DEVICE "pci-express-device" 226 227 /* Implemented by devices that can be plugged on Conventional PCI buses */ 228 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device" 229 230 typedef struct PCIINTxRoute { 231 enum { 232 PCI_INTX_ENABLED, 233 PCI_INTX_INVERTED, 234 PCI_INTX_DISABLED, 235 } mode; 236 int irq; 237 } PCIINTxRoute; 238 239 struct PCIDeviceClass { 240 DeviceClass parent_class; 241 242 void (*realize)(PCIDevice *dev, Error **errp); 243 PCIUnregisterFunc *exit; 244 PCIConfigReadFunc *config_read; 245 PCIConfigWriteFunc *config_write; 246 247 uint16_t vendor_id; 248 uint16_t device_id; 249 uint8_t revision; 250 uint16_t class_id; 251 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 252 uint16_t subsystem_id; /* only for header type = 0 */ 253 254 /* 255 * pci-to-pci bridge or normal device. 256 * This doesn't mean pci host switch. 257 * When card bus bridge is supported, this would be enhanced. 258 */ 259 bool is_bridge; 260 261 /* rom bar */ 262 const char *romfile; 263 }; 264 265 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 266 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 267 MSIMessage msg); 268 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 269 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 270 unsigned int vector_start, 271 unsigned int vector_end); 272 273 enum PCIReqIDType { 274 PCI_REQ_ID_INVALID = 0, 275 PCI_REQ_ID_BDF, 276 PCI_REQ_ID_SECONDARY_BUS, 277 PCI_REQ_ID_MAX, 278 }; 279 typedef enum PCIReqIDType PCIReqIDType; 280 281 struct PCIReqIDCache { 282 PCIDevice *dev; 283 PCIReqIDType type; 284 }; 285 typedef struct PCIReqIDCache PCIReqIDCache; 286 287 struct PCIDevice { 288 DeviceState qdev; 289 bool partially_hotplugged; 290 bool has_power; 291 292 /* PCI config space */ 293 uint8_t *config; 294 295 /* Used to enable config checks on load. Note that writable bits are 296 * never checked even if set in cmask. */ 297 uint8_t *cmask; 298 299 /* Used to implement R/W bytes */ 300 uint8_t *wmask; 301 302 /* Used to implement RW1C(Write 1 to Clear) bytes */ 303 uint8_t *w1cmask; 304 305 /* Used to allocate config space for capabilities. */ 306 uint8_t *used; 307 308 /* the following fields are read only */ 309 int32_t devfn; 310 /* Cached device to fetch requester ID from, to avoid the PCI 311 * tree walking every time we invoke PCI request (e.g., 312 * MSI). For conventional PCI root complex, this field is 313 * meaningless. */ 314 PCIReqIDCache requester_id_cache; 315 char name[64]; 316 PCIIORegion io_regions[PCI_NUM_REGIONS]; 317 AddressSpace bus_master_as; 318 MemoryRegion bus_master_container_region; 319 MemoryRegion bus_master_enable_region; 320 321 /* do not access the following fields */ 322 PCIConfigReadFunc *config_read; 323 PCIConfigWriteFunc *config_write; 324 325 /* Legacy PCI VGA regions */ 326 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 327 bool has_vga; 328 329 /* Current IRQ levels. Used internally by the generic PCI code. */ 330 uint8_t irq_state; 331 332 /* Capability bits */ 333 uint32_t cap_present; 334 335 /* Offset of MSI-X capability in config space */ 336 uint8_t msix_cap; 337 338 /* MSI-X entries */ 339 int msix_entries_nr; 340 341 /* Space to store MSIX table & pending bit array */ 342 uint8_t *msix_table; 343 uint8_t *msix_pba; 344 345 /* May be used by INTx or MSI during interrupt notification */ 346 void *irq_opaque; 347 348 MSITriggerFunc *msi_trigger; 349 MSIPrepareMessageFunc *msi_prepare_message; 350 MSIxPrepareMessageFunc *msix_prepare_message; 351 352 /* MemoryRegion container for msix exclusive BAR setup */ 353 MemoryRegion msix_exclusive_bar; 354 /* Memory Regions for MSIX table and pending bit entries. */ 355 MemoryRegion msix_table_mmio; 356 MemoryRegion msix_pba_mmio; 357 /* Reference-count for entries actually in use by driver. */ 358 unsigned *msix_entry_used; 359 /* MSIX function mask set or MSIX disabled */ 360 bool msix_function_masked; 361 /* Version id needed for VMState */ 362 int32_t version_id; 363 364 /* Offset of MSI capability in config space */ 365 uint8_t msi_cap; 366 367 /* PCI Express */ 368 PCIExpressDevice exp; 369 370 /* SHPC */ 371 SHPCDevice *shpc; 372 373 /* Location of option rom */ 374 char *romfile; 375 uint32_t romsize; 376 bool has_rom; 377 MemoryRegion rom; 378 uint32_t rom_bar; 379 380 /* INTx routing notifier */ 381 PCIINTxRoutingNotifier intx_routing_notifier; 382 383 /* MSI-X notifiers */ 384 MSIVectorUseNotifier msix_vector_use_notifier; 385 MSIVectorReleaseNotifier msix_vector_release_notifier; 386 MSIVectorPollNotifier msix_vector_poll_notifier; 387 388 /* ID of standby device in net_failover pair */ 389 char *failover_pair_id; 390 uint32_t acpi_index; 391 }; 392 393 void pci_register_bar(PCIDevice *pci_dev, int region_num, 394 uint8_t attr, MemoryRegion *memory); 395 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 396 MemoryRegion *io_lo, MemoryRegion *io_hi); 397 void pci_unregister_vga(PCIDevice *pci_dev); 398 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 399 400 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 401 uint8_t offset, uint8_t size, 402 Error **errp); 403 404 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 405 406 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 407 408 409 uint32_t pci_default_read_config(PCIDevice *d, 410 uint32_t address, int len); 411 void pci_default_write_config(PCIDevice *d, 412 uint32_t address, uint32_t val, int len); 413 void pci_device_save(PCIDevice *s, QEMUFile *f); 414 int pci_device_load(PCIDevice *s, QEMUFile *f); 415 MemoryRegion *pci_address_space(PCIDevice *dev); 416 MemoryRegion *pci_address_space_io(PCIDevice *dev); 417 418 /* 419 * Should not normally be used by devices. For use by sPAPR target 420 * where QEMU emulates firmware. 421 */ 422 int pci_bar(PCIDevice *d, int reg); 423 424 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 425 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 426 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 427 428 #define TYPE_PCI_BUS "PCI" 429 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) 430 #define TYPE_PCIE_BUS "PCIE" 431 #define TYPE_CXL_BUS "CXL" 432 433 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque); 434 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque); 435 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque); 436 437 bool pci_bus_is_express(PCIBus *bus); 438 439 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 440 const char *name, 441 MemoryRegion *address_space_mem, 442 MemoryRegion *address_space_io, 443 uint8_t devfn_min, const char *typename); 444 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 445 MemoryRegion *address_space_mem, 446 MemoryRegion *address_space_io, 447 uint8_t devfn_min, const char *typename); 448 void pci_root_bus_cleanup(PCIBus *bus); 449 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 450 void *irq_opaque, int nirq); 451 void pci_bus_irqs_cleanup(PCIBus *bus); 452 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 453 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 454 static inline int pci_swizzle(int slot, int pin) 455 { 456 return (slot + pin) % PCI_NUM_PINS; 457 } 458 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 459 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 460 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 461 void *irq_opaque, 462 MemoryRegion *address_space_mem, 463 MemoryRegion *address_space_io, 464 uint8_t devfn_min, int nirq, 465 const char *typename); 466 void pci_unregister_root_bus(PCIBus *bus); 467 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 468 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 469 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 470 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 471 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 472 PCIINTxRoutingNotifier notifier); 473 void pci_device_reset(PCIDevice *dev); 474 475 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 476 const char *default_model, 477 const char *default_devaddr); 478 479 PCIDevice *pci_vga_init(PCIBus *bus); 480 481 static inline PCIBus *pci_get_bus(const PCIDevice *dev) 482 { 483 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); 484 } 485 int pci_bus_num(PCIBus *s); 486 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus); 487 static inline int pci_dev_bus_num(const PCIDevice *dev) 488 { 489 return pci_bus_num(pci_get_bus(dev)); 490 } 491 492 int pci_bus_numa_node(PCIBus *bus); 493 void pci_for_each_device(PCIBus *bus, int bus_num, 494 pci_bus_dev_fn fn, 495 void *opaque); 496 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 497 pci_bus_dev_fn fn, 498 void *opaque); 499 void pci_for_each_device_under_bus(PCIBus *bus, 500 pci_bus_dev_fn fn, void *opaque); 501 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 502 pci_bus_dev_fn fn, 503 void *opaque); 504 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 505 pci_bus_fn end, void *parent_state); 506 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 507 508 /* Use this wrapper when specific scan order is not required. */ 509 static inline 510 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque) 511 { 512 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 513 } 514 515 PCIBus *pci_device_root_bus(const PCIDevice *d); 516 const char *pci_root_bus_path(PCIDevice *dev); 517 bool pci_bus_bypass_iommu(PCIBus *bus); 518 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 519 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 520 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 521 522 void pci_device_deassert_intx(PCIDevice *dev); 523 524 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 525 526 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 527 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 528 529 pcibus_t pci_bar_address(PCIDevice *d, 530 int reg, uint8_t type, pcibus_t size); 531 532 static inline void 533 pci_set_byte(uint8_t *config, uint8_t val) 534 { 535 *config = val; 536 } 537 538 static inline uint8_t 539 pci_get_byte(const uint8_t *config) 540 { 541 return *config; 542 } 543 544 static inline void 545 pci_set_word(uint8_t *config, uint16_t val) 546 { 547 stw_le_p(config, val); 548 } 549 550 static inline uint16_t 551 pci_get_word(const uint8_t *config) 552 { 553 return lduw_le_p(config); 554 } 555 556 static inline void 557 pci_set_long(uint8_t *config, uint32_t val) 558 { 559 stl_le_p(config, val); 560 } 561 562 static inline uint32_t 563 pci_get_long(const uint8_t *config) 564 { 565 return ldl_le_p(config); 566 } 567 568 /* 569 * PCI capabilities and/or their fields 570 * are generally DWORD aligned only so 571 * mechanism used by pci_set/get_quad() 572 * must be tolerant to unaligned pointers 573 * 574 */ 575 static inline void 576 pci_set_quad(uint8_t *config, uint64_t val) 577 { 578 stq_le_p(config, val); 579 } 580 581 static inline uint64_t 582 pci_get_quad(const uint8_t *config) 583 { 584 return ldq_le_p(config); 585 } 586 587 static inline void 588 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 589 { 590 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 591 } 592 593 static inline void 594 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 595 { 596 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 597 } 598 599 static inline void 600 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 601 { 602 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 603 } 604 605 static inline void 606 pci_config_set_class(uint8_t *pci_config, uint16_t val) 607 { 608 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 609 } 610 611 static inline void 612 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 613 { 614 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 615 } 616 617 static inline void 618 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 619 { 620 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 621 } 622 623 /* 624 * helper functions to do bit mask operation on configuration space. 625 * Just to set bit, use test-and-set and discard returned value. 626 * Just to clear bit, use test-and-clear and discard returned value. 627 * NOTE: They aren't atomic. 628 */ 629 static inline uint8_t 630 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 631 { 632 uint8_t val = pci_get_byte(config); 633 pci_set_byte(config, val & ~mask); 634 return val & mask; 635 } 636 637 static inline uint8_t 638 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 639 { 640 uint8_t val = pci_get_byte(config); 641 pci_set_byte(config, val | mask); 642 return val & mask; 643 } 644 645 static inline uint16_t 646 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 647 { 648 uint16_t val = pci_get_word(config); 649 pci_set_word(config, val & ~mask); 650 return val & mask; 651 } 652 653 static inline uint16_t 654 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 655 { 656 uint16_t val = pci_get_word(config); 657 pci_set_word(config, val | mask); 658 return val & mask; 659 } 660 661 static inline uint32_t 662 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 663 { 664 uint32_t val = pci_get_long(config); 665 pci_set_long(config, val & ~mask); 666 return val & mask; 667 } 668 669 static inline uint32_t 670 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 671 { 672 uint32_t val = pci_get_long(config); 673 pci_set_long(config, val | mask); 674 return val & mask; 675 } 676 677 static inline uint64_t 678 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 679 { 680 uint64_t val = pci_get_quad(config); 681 pci_set_quad(config, val & ~mask); 682 return val & mask; 683 } 684 685 static inline uint64_t 686 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 687 { 688 uint64_t val = pci_get_quad(config); 689 pci_set_quad(config, val | mask); 690 return val & mask; 691 } 692 693 /* Access a register specified by a mask */ 694 static inline void 695 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 696 { 697 uint8_t val = pci_get_byte(config); 698 uint8_t rval; 699 700 assert(mask); 701 rval = reg << ctz32(mask); 702 pci_set_byte(config, (~mask & val) | (mask & rval)); 703 } 704 705 static inline void 706 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 707 { 708 uint16_t val = pci_get_word(config); 709 uint16_t rval; 710 711 assert(mask); 712 rval = reg << ctz32(mask); 713 pci_set_word(config, (~mask & val) | (mask & rval)); 714 } 715 716 static inline void 717 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 718 { 719 uint32_t val = pci_get_long(config); 720 uint32_t rval; 721 722 assert(mask); 723 rval = reg << ctz32(mask); 724 pci_set_long(config, (~mask & val) | (mask & rval)); 725 } 726 727 static inline void 728 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 729 { 730 uint64_t val = pci_get_quad(config); 731 uint64_t rval; 732 733 assert(mask); 734 rval = reg << ctz32(mask); 735 pci_set_quad(config, (~mask & val) | (mask & rval)); 736 } 737 738 PCIDevice *pci_new_multifunction(int devfn, bool multifunction, 739 const char *name); 740 PCIDevice *pci_new(int devfn, const char *name); 741 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); 742 743 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 744 bool multifunction, 745 const char *name); 746 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 747 748 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); 749 750 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 751 void pci_set_irq(PCIDevice *pci_dev, int level); 752 753 static inline int pci_intx(PCIDevice *pci_dev) 754 { 755 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 756 } 757 758 static inline void pci_irq_assert(PCIDevice *pci_dev) 759 { 760 pci_set_irq(pci_dev, 1); 761 } 762 763 static inline void pci_irq_deassert(PCIDevice *pci_dev) 764 { 765 pci_set_irq(pci_dev, 0); 766 } 767 768 /* 769 * FIXME: PCI does not work this way. 770 * All the callers to this method should be fixed. 771 */ 772 static inline void pci_irq_pulse(PCIDevice *pci_dev) 773 { 774 pci_irq_assert(pci_dev); 775 pci_irq_deassert(pci_dev); 776 } 777 778 static inline int pci_is_cxl(const PCIDevice *d) 779 { 780 return d->cap_present & QEMU_PCIE_CAP_CXL; 781 } 782 783 static inline int pci_is_express(const PCIDevice *d) 784 { 785 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 786 } 787 788 static inline int pci_is_express_downstream_port(const PCIDevice *d) 789 { 790 uint8_t type; 791 792 if (!pci_is_express(d) || !d->exp.exp_cap) { 793 return 0; 794 } 795 796 type = pcie_cap_get_type(d); 797 798 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT; 799 } 800 801 static inline int pci_is_vf(const PCIDevice *d) 802 { 803 return d->exp.sriov_vf.pf != NULL; 804 } 805 806 static inline uint32_t pci_config_size(const PCIDevice *d) 807 { 808 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 809 } 810 811 static inline uint16_t pci_get_bdf(PCIDevice *dev) 812 { 813 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn); 814 } 815 816 uint16_t pci_requester_id(PCIDevice *dev); 817 818 /* DMA access functions */ 819 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 820 { 821 return &dev->bus_master_as; 822 } 823 824 /** 825 * pci_dma_rw: Read from or write to an address space from PCI device. 826 * 827 * Return a MemTxResult indicating whether the operation succeeded 828 * or failed (eg unassigned memory, device rejected the transaction, 829 * IOMMU fault). 830 * 831 * @dev: #PCIDevice doing the memory access 832 * @addr: address within the #PCIDevice address space 833 * @buf: buffer with the data transferred 834 * @len: the number of bytes to read or write 835 * @dir: indicates the transfer direction 836 */ 837 static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 838 void *buf, dma_addr_t len, 839 DMADirection dir, MemTxAttrs attrs) 840 { 841 return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, 842 dir, attrs); 843 } 844 845 /** 846 * pci_dma_read: Read from an address space from PCI device. 847 * 848 * Return a MemTxResult indicating whether the operation succeeded 849 * or failed (eg unassigned memory, device rejected the transaction, 850 * IOMMU fault). Called within RCU critical section. 851 * 852 * @dev: #PCIDevice doing the memory access 853 * @addr: address within the #PCIDevice address space 854 * @buf: buffer with the data transferred 855 * @len: length of the data transferred 856 */ 857 static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr, 858 void *buf, dma_addr_t len) 859 { 860 return pci_dma_rw(dev, addr, buf, len, 861 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); 862 } 863 864 /** 865 * pci_dma_write: Write to address space from PCI device. 866 * 867 * Return a MemTxResult indicating whether the operation succeeded 868 * or failed (eg unassigned memory, device rejected the transaction, 869 * IOMMU fault). 870 * 871 * @dev: #PCIDevice doing the memory access 872 * @addr: address within the #PCIDevice address space 873 * @buf: buffer with the data transferred 874 * @len: the number of bytes to write 875 */ 876 static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr, 877 const void *buf, dma_addr_t len) 878 { 879 return pci_dma_rw(dev, addr, (void *) buf, len, 880 DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED); 881 } 882 883 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 884 static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \ 885 dma_addr_t addr, \ 886 uint##_bits##_t *val, \ 887 MemTxAttrs attrs) \ 888 { \ 889 return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \ 890 } \ 891 static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \ 892 dma_addr_t addr, \ 893 uint##_bits##_t val, \ 894 MemTxAttrs attrs) \ 895 { \ 896 return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \ 897 } 898 899 PCI_DMA_DEFINE_LDST(ub, b, 8); 900 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 901 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 902 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 903 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 904 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 905 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 906 907 #undef PCI_DMA_DEFINE_LDST 908 909 /** 910 * pci_dma_map: Map device PCI address space range into host virtual address 911 * @dev: #PCIDevice to be accessed 912 * @addr: address within that device's address space 913 * @plen: pointer to length of buffer; updated on return to indicate 914 * if only a subset of the requested range has been mapped 915 * @dir: indicates the transfer direction 916 * 917 * Return: A host pointer, or %NULL if the resources needed to 918 * perform the mapping are exhausted (in that case *@plen 919 * is set to zero). 920 */ 921 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 922 dma_addr_t *plen, DMADirection dir) 923 { 924 void *buf; 925 926 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir, 927 MEMTXATTRS_UNSPECIFIED); 928 return buf; 929 } 930 931 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 932 DMADirection dir, dma_addr_t access_len) 933 { 934 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 935 } 936 937 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 938 int alloc_hint) 939 { 940 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 941 } 942 943 extern const VMStateDescription vmstate_pci_device; 944 945 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 946 .name = (stringify(_field)), \ 947 .size = sizeof(PCIDevice), \ 948 .vmsd = &vmstate_pci_device, \ 949 .flags = VMS_STRUCT, \ 950 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 951 } 952 953 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 954 .name = (stringify(_field)), \ 955 .size = sizeof(PCIDevice), \ 956 .vmsd = &vmstate_pci_device, \ 957 .flags = VMS_STRUCT|VMS_POINTER, \ 958 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 959 } 960 961 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 962 void pci_set_power(PCIDevice *pci_dev, bool state); 963 964 #endif 965