1 #ifndef QEMU_PCI_H 2 #define QEMU_PCI_H 3 4 #include "exec/memory.h" 5 #include "sysemu/dma.h" 6 7 /* PCI includes legacy ISA access. */ 8 #include "hw/isa/isa.h" 9 10 extern bool pci_available; 11 12 /* PCI bus */ 13 14 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 15 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 16 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 17 #define PCI_FUNC(devfn) ((devfn) & 0x07) 18 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) 19 #define PCI_BUS_MAX 256 20 #define PCI_DEVFN_MAX 256 21 #define PCI_SLOT_MAX 32 22 #define PCI_FUNC_MAX 8 23 24 /* Class, Vendor and Device IDs from Linux's pci_ids.h */ 25 #include "hw/pci/pci_ids.h" 26 27 /* QEMU-specific Vendor and Device ID definitions */ 28 29 /* IBM (0x1014) */ 30 #define PCI_DEVICE_ID_IBM_440GX 0x027f 31 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff 32 33 /* Hitachi (0x1054) */ 34 #define PCI_VENDOR_ID_HITACHI 0x1054 35 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e 36 37 /* Apple (0x106b) */ 38 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 39 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e 40 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f 41 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 42 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f 43 44 /* Realtek (0x10ec) */ 45 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 46 47 /* Xilinx (0x10ee) */ 48 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 49 50 /* Marvell (0x11ab) */ 51 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 52 53 /* QEMU/Bochs VGA (0x1234) */ 54 #define PCI_VENDOR_ID_QEMU 0x1234 55 #define PCI_DEVICE_ID_QEMU_VGA 0x1111 56 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 57 58 /* VMWare (0x15ad) */ 59 #define PCI_VENDOR_ID_VMWARE 0x15ad 60 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 61 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 62 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 63 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 64 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 65 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 66 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 67 68 /* Intel (0x8086) */ 69 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 70 #define PCI_DEVICE_ID_INTEL_82557 0x1229 71 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 72 73 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ 74 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 75 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 76 #define PCI_SUBDEVICE_ID_QEMU 0x1100 77 78 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 79 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 80 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 81 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 82 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 83 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 84 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 85 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 86 #define PCI_DEVICE_ID_VIRTIO_PMEM 0x1013 87 #define PCI_DEVICE_ID_VIRTIO_IOMMU 0x1014 88 #define PCI_DEVICE_ID_VIRTIO_MEM 0x1015 89 90 #define PCI_VENDOR_ID_REDHAT 0x1b36 91 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 92 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 93 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 94 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 95 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 96 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 97 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 98 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 99 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 100 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a 101 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b 102 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c 103 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d 104 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e 105 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f 106 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010 107 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011 108 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012 109 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 110 111 #define FMT_PCIBUS PRIx64 112 113 typedef uint64_t pcibus_t; 114 115 struct PCIHostDeviceAddress { 116 unsigned int domain; 117 unsigned int bus; 118 unsigned int slot; 119 unsigned int function; 120 }; 121 122 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 123 uint32_t address, uint32_t data, int len); 124 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 125 uint32_t address, int len); 126 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 127 pcibus_t addr, pcibus_t size, int type); 128 typedef void PCIUnregisterFunc(PCIDevice *pci_dev); 129 130 typedef struct PCIIORegion { 131 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ 132 #define PCI_BAR_UNMAPPED (~(pcibus_t)0) 133 pcibus_t size; 134 uint8_t type; 135 MemoryRegion *memory; 136 MemoryRegion *address_space; 137 } PCIIORegion; 138 139 #define PCI_ROM_SLOT 6 140 #define PCI_NUM_REGIONS 7 141 142 enum { 143 QEMU_PCI_VGA_MEM, 144 QEMU_PCI_VGA_IO_LO, 145 QEMU_PCI_VGA_IO_HI, 146 QEMU_PCI_VGA_NUM_REGIONS, 147 }; 148 149 #define QEMU_PCI_VGA_MEM_BASE 0xa0000 150 #define QEMU_PCI_VGA_MEM_SIZE 0x20000 151 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 152 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc 153 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 154 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 155 156 #include "hw/pci/pci_regs.h" 157 #include "hw/pci/pcie.h" 158 159 /* PCI HEADER_TYPE */ 160 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 161 162 /* Size of the standard PCI config header */ 163 #define PCI_CONFIG_HEADER_SIZE 0x40 164 /* Size of the standard PCI config space */ 165 #define PCI_CONFIG_SPACE_SIZE 0x100 166 /* Size of the standard PCIe config space: 4KB */ 167 #define PCIE_CONFIG_SPACE_SIZE 0x1000 168 169 #define PCI_NUM_PINS 4 /* A-D */ 170 171 /* Bits in cap_present field. */ 172 enum { 173 QEMU_PCI_CAP_MSI = 0x1, 174 QEMU_PCI_CAP_MSIX = 0x2, 175 QEMU_PCI_CAP_EXPRESS = 0x4, 176 177 /* multifunction capable device */ 178 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 179 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), 180 181 /* command register SERR bit enabled - unused since QEMU v5.0 */ 182 #define QEMU_PCI_CAP_SERR_BITNR 4 183 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), 184 /* Standard hot plug controller. */ 185 #define QEMU_PCI_SHPC_BITNR 5 186 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), 187 #define QEMU_PCI_SLOTID_BITNR 6 188 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), 189 /* PCI Express capability - Power Controller Present */ 190 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 191 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), 192 /* Link active status in endpoint capability is always set */ 193 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 194 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), 195 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 196 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), 197 #define QEMU_PCIE_CXL_BITNR 10 198 QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR), 199 }; 200 201 #define TYPE_PCI_DEVICE "pci-device" 202 typedef struct PCIDeviceClass PCIDeviceClass; 203 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass, 204 PCI_DEVICE, TYPE_PCI_DEVICE) 205 206 /* 207 * Implemented by devices that can be plugged on CXL buses. In the spec, this is 208 * actually a "CXL Component, but we name it device to match the PCI naming. 209 */ 210 #define INTERFACE_CXL_DEVICE "cxl-device" 211 212 /* Implemented by devices that can be plugged on PCI Express buses */ 213 #define INTERFACE_PCIE_DEVICE "pci-express-device" 214 215 /* Implemented by devices that can be plugged on Conventional PCI buses */ 216 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device" 217 218 typedef struct PCIINTxRoute { 219 enum { 220 PCI_INTX_ENABLED, 221 PCI_INTX_INVERTED, 222 PCI_INTX_DISABLED, 223 } mode; 224 int irq; 225 } PCIINTxRoute; 226 227 struct PCIDeviceClass { 228 DeviceClass parent_class; 229 230 void (*realize)(PCIDevice *dev, Error **errp); 231 PCIUnregisterFunc *exit; 232 PCIConfigReadFunc *config_read; 233 PCIConfigWriteFunc *config_write; 234 235 uint16_t vendor_id; 236 uint16_t device_id; 237 uint8_t revision; 238 uint16_t class_id; 239 uint16_t subsystem_vendor_id; /* only for header type = 0 */ 240 uint16_t subsystem_id; /* only for header type = 0 */ 241 242 /* 243 * pci-to-pci bridge or normal device. 244 * This doesn't mean pci host switch. 245 * When card bus bridge is supported, this would be enhanced. 246 */ 247 bool is_bridge; 248 249 /* rom bar */ 250 const char *romfile; 251 }; 252 253 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); 254 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, 255 MSIMessage msg); 256 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); 257 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, 258 unsigned int vector_start, 259 unsigned int vector_end); 260 261 enum PCIReqIDType { 262 PCI_REQ_ID_INVALID = 0, 263 PCI_REQ_ID_BDF, 264 PCI_REQ_ID_SECONDARY_BUS, 265 PCI_REQ_ID_MAX, 266 }; 267 typedef enum PCIReqIDType PCIReqIDType; 268 269 struct PCIReqIDCache { 270 PCIDevice *dev; 271 PCIReqIDType type; 272 }; 273 typedef struct PCIReqIDCache PCIReqIDCache; 274 275 struct PCIDevice { 276 DeviceState qdev; 277 bool partially_hotplugged; 278 bool has_power; 279 280 /* PCI config space */ 281 uint8_t *config; 282 283 /* Used to enable config checks on load. Note that writable bits are 284 * never checked even if set in cmask. */ 285 uint8_t *cmask; 286 287 /* Used to implement R/W bytes */ 288 uint8_t *wmask; 289 290 /* Used to implement RW1C(Write 1 to Clear) bytes */ 291 uint8_t *w1cmask; 292 293 /* Used to allocate config space for capabilities. */ 294 uint8_t *used; 295 296 /* the following fields are read only */ 297 int32_t devfn; 298 /* Cached device to fetch requester ID from, to avoid the PCI 299 * tree walking every time we invoke PCI request (e.g., 300 * MSI). For conventional PCI root complex, this field is 301 * meaningless. */ 302 PCIReqIDCache requester_id_cache; 303 char name[64]; 304 PCIIORegion io_regions[PCI_NUM_REGIONS]; 305 AddressSpace bus_master_as; 306 MemoryRegion bus_master_container_region; 307 MemoryRegion bus_master_enable_region; 308 309 /* do not access the following fields */ 310 PCIConfigReadFunc *config_read; 311 PCIConfigWriteFunc *config_write; 312 313 /* Legacy PCI VGA regions */ 314 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; 315 bool has_vga; 316 317 /* Current IRQ levels. Used internally by the generic PCI code. */ 318 uint8_t irq_state; 319 320 /* Capability bits */ 321 uint32_t cap_present; 322 323 /* Offset of MSI-X capability in config space */ 324 uint8_t msix_cap; 325 326 /* MSI-X entries */ 327 int msix_entries_nr; 328 329 /* Space to store MSIX table & pending bit array */ 330 uint8_t *msix_table; 331 uint8_t *msix_pba; 332 /* MemoryRegion container for msix exclusive BAR setup */ 333 MemoryRegion msix_exclusive_bar; 334 /* Memory Regions for MSIX table and pending bit entries. */ 335 MemoryRegion msix_table_mmio; 336 MemoryRegion msix_pba_mmio; 337 /* Reference-count for entries actually in use by driver. */ 338 unsigned *msix_entry_used; 339 /* MSIX function mask set or MSIX disabled */ 340 bool msix_function_masked; 341 /* Version id needed for VMState */ 342 int32_t version_id; 343 344 /* Offset of MSI capability in config space */ 345 uint8_t msi_cap; 346 347 /* PCI Express */ 348 PCIExpressDevice exp; 349 350 /* SHPC */ 351 SHPCDevice *shpc; 352 353 /* Location of option rom */ 354 char *romfile; 355 uint32_t romsize; 356 bool has_rom; 357 MemoryRegion rom; 358 uint32_t rom_bar; 359 360 /* INTx routing notifier */ 361 PCIINTxRoutingNotifier intx_routing_notifier; 362 363 /* MSI-X notifiers */ 364 MSIVectorUseNotifier msix_vector_use_notifier; 365 MSIVectorReleaseNotifier msix_vector_release_notifier; 366 MSIVectorPollNotifier msix_vector_poll_notifier; 367 368 /* ID of standby device in net_failover pair */ 369 char *failover_pair_id; 370 uint32_t acpi_index; 371 }; 372 373 void pci_register_bar(PCIDevice *pci_dev, int region_num, 374 uint8_t attr, MemoryRegion *memory); 375 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 376 MemoryRegion *io_lo, MemoryRegion *io_hi); 377 void pci_unregister_vga(PCIDevice *pci_dev); 378 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); 379 380 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 381 uint8_t offset, uint8_t size, 382 Error **errp); 383 384 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); 385 386 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); 387 388 389 uint32_t pci_default_read_config(PCIDevice *d, 390 uint32_t address, int len); 391 void pci_default_write_config(PCIDevice *d, 392 uint32_t address, uint32_t val, int len); 393 void pci_device_save(PCIDevice *s, QEMUFile *f); 394 int pci_device_load(PCIDevice *s, QEMUFile *f); 395 MemoryRegion *pci_address_space(PCIDevice *dev); 396 MemoryRegion *pci_address_space_io(PCIDevice *dev); 397 398 /* 399 * Should not normally be used by devices. For use by sPAPR target 400 * where QEMU emulates firmware. 401 */ 402 int pci_bar(PCIDevice *d, int reg); 403 404 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); 405 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); 406 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 407 408 #define TYPE_PCI_BUS "PCI" 409 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) 410 #define TYPE_PCIE_BUS "PCIE" 411 #define TYPE_CXL_BUS "CXL" 412 413 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque); 414 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque); 415 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque); 416 417 bool pci_bus_is_express(PCIBus *bus); 418 419 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 420 const char *name, 421 MemoryRegion *address_space_mem, 422 MemoryRegion *address_space_io, 423 uint8_t devfn_min, const char *typename); 424 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 425 MemoryRegion *address_space_mem, 426 MemoryRegion *address_space_io, 427 uint8_t devfn_min, const char *typename); 428 void pci_root_bus_cleanup(PCIBus *bus); 429 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 430 void *irq_opaque, int nirq); 431 void pci_bus_irqs_cleanup(PCIBus *bus); 432 int pci_bus_get_irq_level(PCIBus *bus, int irq_num); 433 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ 434 static inline int pci_swizzle(int slot, int pin) 435 { 436 return (slot + pin) % PCI_NUM_PINS; 437 } 438 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 439 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 440 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 441 void *irq_opaque, 442 MemoryRegion *address_space_mem, 443 MemoryRegion *address_space_io, 444 uint8_t devfn_min, int nirq, 445 const char *typename); 446 void pci_unregister_root_bus(PCIBus *bus); 447 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); 448 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); 449 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); 450 void pci_bus_fire_intx_routing_notifier(PCIBus *bus); 451 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 452 PCIINTxRoutingNotifier notifier); 453 void pci_device_reset(PCIDevice *dev); 454 455 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 456 const char *default_model, 457 const char *default_devaddr); 458 459 PCIDevice *pci_vga_init(PCIBus *bus); 460 461 static inline PCIBus *pci_get_bus(const PCIDevice *dev) 462 { 463 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); 464 } 465 int pci_bus_num(PCIBus *s); 466 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus); 467 static inline int pci_dev_bus_num(const PCIDevice *dev) 468 { 469 return pci_bus_num(pci_get_bus(dev)); 470 } 471 472 int pci_bus_numa_node(PCIBus *bus); 473 void pci_for_each_device(PCIBus *bus, int bus_num, 474 pci_bus_dev_fn fn, 475 void *opaque); 476 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 477 pci_bus_dev_fn fn, 478 void *opaque); 479 void pci_for_each_device_under_bus(PCIBus *bus, 480 pci_bus_dev_fn fn, void *opaque); 481 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 482 pci_bus_dev_fn fn, 483 void *opaque); 484 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 485 pci_bus_fn end, void *parent_state); 486 PCIDevice *pci_get_function_0(PCIDevice *pci_dev); 487 488 /* Use this wrapper when specific scan order is not required. */ 489 static inline 490 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque) 491 { 492 pci_for_each_bus_depth_first(bus, NULL, fn, opaque); 493 } 494 495 PCIBus *pci_device_root_bus(const PCIDevice *d); 496 const char *pci_root_bus_path(PCIDevice *dev); 497 bool pci_bus_bypass_iommu(PCIBus *bus); 498 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); 499 int pci_qdev_find_device(const char *id, PCIDevice **pdev); 500 void pci_bus_get_w64_range(PCIBus *bus, Range *range); 501 502 void pci_device_deassert_intx(PCIDevice *dev); 503 504 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); 505 506 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); 507 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); 508 509 pcibus_t pci_bar_address(PCIDevice *d, 510 int reg, uint8_t type, pcibus_t size); 511 512 static inline void 513 pci_set_byte(uint8_t *config, uint8_t val) 514 { 515 *config = val; 516 } 517 518 static inline uint8_t 519 pci_get_byte(const uint8_t *config) 520 { 521 return *config; 522 } 523 524 static inline void 525 pci_set_word(uint8_t *config, uint16_t val) 526 { 527 stw_le_p(config, val); 528 } 529 530 static inline uint16_t 531 pci_get_word(const uint8_t *config) 532 { 533 return lduw_le_p(config); 534 } 535 536 static inline void 537 pci_set_long(uint8_t *config, uint32_t val) 538 { 539 stl_le_p(config, val); 540 } 541 542 static inline uint32_t 543 pci_get_long(const uint8_t *config) 544 { 545 return ldl_le_p(config); 546 } 547 548 /* 549 * PCI capabilities and/or their fields 550 * are generally DWORD aligned only so 551 * mechanism used by pci_set/get_quad() 552 * must be tolerant to unaligned pointers 553 * 554 */ 555 static inline void 556 pci_set_quad(uint8_t *config, uint64_t val) 557 { 558 stq_le_p(config, val); 559 } 560 561 static inline uint64_t 562 pci_get_quad(const uint8_t *config) 563 { 564 return ldq_le_p(config); 565 } 566 567 static inline void 568 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) 569 { 570 pci_set_word(&pci_config[PCI_VENDOR_ID], val); 571 } 572 573 static inline void 574 pci_config_set_device_id(uint8_t *pci_config, uint16_t val) 575 { 576 pci_set_word(&pci_config[PCI_DEVICE_ID], val); 577 } 578 579 static inline void 580 pci_config_set_revision(uint8_t *pci_config, uint8_t val) 581 { 582 pci_set_byte(&pci_config[PCI_REVISION_ID], val); 583 } 584 585 static inline void 586 pci_config_set_class(uint8_t *pci_config, uint16_t val) 587 { 588 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); 589 } 590 591 static inline void 592 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) 593 { 594 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); 595 } 596 597 static inline void 598 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) 599 { 600 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); 601 } 602 603 /* 604 * helper functions to do bit mask operation on configuration space. 605 * Just to set bit, use test-and-set and discard returned value. 606 * Just to clear bit, use test-and-clear and discard returned value. 607 * NOTE: They aren't atomic. 608 */ 609 static inline uint8_t 610 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) 611 { 612 uint8_t val = pci_get_byte(config); 613 pci_set_byte(config, val & ~mask); 614 return val & mask; 615 } 616 617 static inline uint8_t 618 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) 619 { 620 uint8_t val = pci_get_byte(config); 621 pci_set_byte(config, val | mask); 622 return val & mask; 623 } 624 625 static inline uint16_t 626 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) 627 { 628 uint16_t val = pci_get_word(config); 629 pci_set_word(config, val & ~mask); 630 return val & mask; 631 } 632 633 static inline uint16_t 634 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) 635 { 636 uint16_t val = pci_get_word(config); 637 pci_set_word(config, val | mask); 638 return val & mask; 639 } 640 641 static inline uint32_t 642 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) 643 { 644 uint32_t val = pci_get_long(config); 645 pci_set_long(config, val & ~mask); 646 return val & mask; 647 } 648 649 static inline uint32_t 650 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) 651 { 652 uint32_t val = pci_get_long(config); 653 pci_set_long(config, val | mask); 654 return val & mask; 655 } 656 657 static inline uint64_t 658 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) 659 { 660 uint64_t val = pci_get_quad(config); 661 pci_set_quad(config, val & ~mask); 662 return val & mask; 663 } 664 665 static inline uint64_t 666 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) 667 { 668 uint64_t val = pci_get_quad(config); 669 pci_set_quad(config, val | mask); 670 return val & mask; 671 } 672 673 /* Access a register specified by a mask */ 674 static inline void 675 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) 676 { 677 uint8_t val = pci_get_byte(config); 678 uint8_t rval = reg << ctz32(mask); 679 pci_set_byte(config, (~mask & val) | (mask & rval)); 680 } 681 682 static inline uint8_t 683 pci_get_byte_by_mask(uint8_t *config, uint8_t mask) 684 { 685 uint8_t val = pci_get_byte(config); 686 return (val & mask) >> ctz32(mask); 687 } 688 689 static inline void 690 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) 691 { 692 uint16_t val = pci_get_word(config); 693 uint16_t rval = reg << ctz32(mask); 694 pci_set_word(config, (~mask & val) | (mask & rval)); 695 } 696 697 static inline uint16_t 698 pci_get_word_by_mask(uint8_t *config, uint16_t mask) 699 { 700 uint16_t val = pci_get_word(config); 701 return (val & mask) >> ctz32(mask); 702 } 703 704 static inline void 705 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) 706 { 707 uint32_t val = pci_get_long(config); 708 uint32_t rval = reg << ctz32(mask); 709 pci_set_long(config, (~mask & val) | (mask & rval)); 710 } 711 712 static inline uint32_t 713 pci_get_long_by_mask(uint8_t *config, uint32_t mask) 714 { 715 uint32_t val = pci_get_long(config); 716 return (val & mask) >> ctz32(mask); 717 } 718 719 static inline void 720 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) 721 { 722 uint64_t val = pci_get_quad(config); 723 uint64_t rval = reg << ctz32(mask); 724 pci_set_quad(config, (~mask & val) | (mask & rval)); 725 } 726 727 static inline uint64_t 728 pci_get_quad_by_mask(uint8_t *config, uint64_t mask) 729 { 730 uint64_t val = pci_get_quad(config); 731 return (val & mask) >> ctz32(mask); 732 } 733 734 PCIDevice *pci_new_multifunction(int devfn, bool multifunction, 735 const char *name); 736 PCIDevice *pci_new(int devfn, const char *name); 737 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); 738 739 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 740 bool multifunction, 741 const char *name); 742 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); 743 744 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); 745 746 qemu_irq pci_allocate_irq(PCIDevice *pci_dev); 747 void pci_set_irq(PCIDevice *pci_dev, int level); 748 749 static inline int pci_intx(PCIDevice *pci_dev) 750 { 751 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 752 } 753 754 static inline void pci_irq_assert(PCIDevice *pci_dev) 755 { 756 pci_set_irq(pci_dev, 1); 757 } 758 759 static inline void pci_irq_deassert(PCIDevice *pci_dev) 760 { 761 pci_set_irq(pci_dev, 0); 762 } 763 764 /* 765 * FIXME: PCI does not work this way. 766 * All the callers to this method should be fixed. 767 */ 768 static inline void pci_irq_pulse(PCIDevice *pci_dev) 769 { 770 pci_irq_assert(pci_dev); 771 pci_irq_deassert(pci_dev); 772 } 773 774 static inline int pci_is_cxl(const PCIDevice *d) 775 { 776 return d->cap_present & QEMU_PCIE_CAP_CXL; 777 } 778 779 static inline int pci_is_express(const PCIDevice *d) 780 { 781 return d->cap_present & QEMU_PCI_CAP_EXPRESS; 782 } 783 784 static inline int pci_is_express_downstream_port(const PCIDevice *d) 785 { 786 uint8_t type; 787 788 if (!pci_is_express(d) || !d->exp.exp_cap) { 789 return 0; 790 } 791 792 type = pcie_cap_get_type(d); 793 794 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT; 795 } 796 797 static inline int pci_is_vf(const PCIDevice *d) 798 { 799 return d->exp.sriov_vf.pf != NULL; 800 } 801 802 static inline uint32_t pci_config_size(const PCIDevice *d) 803 { 804 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; 805 } 806 807 static inline uint16_t pci_get_bdf(PCIDevice *dev) 808 { 809 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn); 810 } 811 812 uint16_t pci_requester_id(PCIDevice *dev); 813 814 /* DMA access functions */ 815 static inline AddressSpace *pci_get_address_space(PCIDevice *dev) 816 { 817 return &dev->bus_master_as; 818 } 819 820 /** 821 * pci_dma_rw: Read from or write to an address space from PCI device. 822 * 823 * Return a MemTxResult indicating whether the operation succeeded 824 * or failed (eg unassigned memory, device rejected the transaction, 825 * IOMMU fault). 826 * 827 * @dev: #PCIDevice doing the memory access 828 * @addr: address within the #PCIDevice address space 829 * @buf: buffer with the data transferred 830 * @len: the number of bytes to read or write 831 * @dir: indicates the transfer direction 832 */ 833 static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr, 834 void *buf, dma_addr_t len, 835 DMADirection dir, MemTxAttrs attrs) 836 { 837 return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, 838 dir, attrs); 839 } 840 841 /** 842 * pci_dma_read: Read from an address space from PCI device. 843 * 844 * Return a MemTxResult indicating whether the operation succeeded 845 * or failed (eg unassigned memory, device rejected the transaction, 846 * IOMMU fault). Called within RCU critical section. 847 * 848 * @dev: #PCIDevice doing the memory access 849 * @addr: address within the #PCIDevice address space 850 * @buf: buffer with the data transferred 851 * @len: length of the data transferred 852 */ 853 static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr, 854 void *buf, dma_addr_t len) 855 { 856 return pci_dma_rw(dev, addr, buf, len, 857 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); 858 } 859 860 /** 861 * pci_dma_write: Write to address space from PCI device. 862 * 863 * Return a MemTxResult indicating whether the operation succeeded 864 * or failed (eg unassigned memory, device rejected the transaction, 865 * IOMMU fault). 866 * 867 * @dev: #PCIDevice doing the memory access 868 * @addr: address within the #PCIDevice address space 869 * @buf: buffer with the data transferred 870 * @len: the number of bytes to write 871 */ 872 static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr, 873 const void *buf, dma_addr_t len) 874 { 875 return pci_dma_rw(dev, addr, (void *) buf, len, 876 DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED); 877 } 878 879 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ 880 static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \ 881 dma_addr_t addr, \ 882 uint##_bits##_t *val, \ 883 MemTxAttrs attrs) \ 884 { \ 885 return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \ 886 } \ 887 static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \ 888 dma_addr_t addr, \ 889 uint##_bits##_t val, \ 890 MemTxAttrs attrs) \ 891 { \ 892 return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \ 893 } 894 895 PCI_DMA_DEFINE_LDST(ub, b, 8); 896 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) 897 PCI_DMA_DEFINE_LDST(l_le, l_le, 32); 898 PCI_DMA_DEFINE_LDST(q_le, q_le, 64); 899 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) 900 PCI_DMA_DEFINE_LDST(l_be, l_be, 32); 901 PCI_DMA_DEFINE_LDST(q_be, q_be, 64); 902 903 #undef PCI_DMA_DEFINE_LDST 904 905 /** 906 * pci_dma_map: Map device PCI address space range into host virtual address 907 * @dev: #PCIDevice to be accessed 908 * @addr: address within that device's address space 909 * @plen: pointer to length of buffer; updated on return to indicate 910 * if only a subset of the requested range has been mapped 911 * @dir: indicates the transfer direction 912 * 913 * Return: A host pointer, or %NULL if the resources needed to 914 * perform the mapping are exhausted (in that case *@plen 915 * is set to zero). 916 */ 917 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, 918 dma_addr_t *plen, DMADirection dir) 919 { 920 void *buf; 921 922 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir, 923 MEMTXATTRS_UNSPECIFIED); 924 return buf; 925 } 926 927 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, 928 DMADirection dir, dma_addr_t access_len) 929 { 930 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); 931 } 932 933 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, 934 int alloc_hint) 935 { 936 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); 937 } 938 939 extern const VMStateDescription vmstate_pci_device; 940 941 #define VMSTATE_PCI_DEVICE(_field, _state) { \ 942 .name = (stringify(_field)), \ 943 .size = sizeof(PCIDevice), \ 944 .vmsd = &vmstate_pci_device, \ 945 .flags = VMS_STRUCT, \ 946 .offset = vmstate_offset_value(_state, _field, PCIDevice), \ 947 } 948 949 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ 950 .name = (stringify(_field)), \ 951 .size = sizeof(PCIDevice), \ 952 .vmsd = &vmstate_pci_device, \ 953 .flags = VMS_STRUCT|VMS_POINTER, \ 954 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ 955 } 956 957 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); 958 void pci_set_power(PCIDevice *pci_dev, bool state); 959 960 #endif 961