1 #ifndef QEMU_PCI_BUS_H 2 #define QEMU_PCI_BUS_H 3 4 /* 5 * PCI Bus and Bridge datastructures. 6 * 7 * Do not access the following members directly; 8 * use accessor functions in pci.h, pci_bridge.h 9 */ 10 11 typedef struct PCIBusClass { 12 /*< private >*/ 13 BusClass parent_class; 14 /*< public >*/ 15 16 bool (*is_root)(PCIBus *bus); 17 int (*bus_num)(PCIBus *bus); 18 uint16_t (*numa_node)(PCIBus *bus); 19 } PCIBusClass; 20 21 struct PCIBus { 22 BusState qbus; 23 PCIIOMMUFunc iommu_fn; 24 void *iommu_opaque; 25 uint8_t devfn_min; 26 pci_set_irq_fn set_irq; 27 pci_map_irq_fn map_irq; 28 pci_route_irq_fn route_intx_to_irq; 29 void *irq_opaque; 30 PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX]; 31 PCIDevice *parent_dev; 32 MemoryRegion *address_space_mem; 33 MemoryRegion *address_space_io; 34 35 QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */ 36 QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */ 37 38 /* The bus IRQ state is the logical OR of the connected devices. 39 Keep a count of the number of devices with raised IRQs. */ 40 int nirq; 41 int *irq_count; 42 43 Notifier machine_done; 44 }; 45 46 typedef struct PCIBridgeWindows PCIBridgeWindows; 47 48 /* 49 * Aliases for each of the address space windows that the bridge 50 * can forward. Mapped into the bridge's parent's address space, 51 * as subregions. 52 */ 53 struct PCIBridgeWindows { 54 MemoryRegion alias_pref_mem; 55 MemoryRegion alias_mem; 56 MemoryRegion alias_io; 57 /* 58 * When bridge control VGA forwarding is enabled, bridges will 59 * provide positive decode on the PCI VGA defined I/O port and 60 * MMIO ranges. When enabled forwarding is only qualified on the 61 * I/O and memory enable bits in the bridge command register. 62 */ 63 MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS]; 64 }; 65 66 #define TYPE_PCI_BRIDGE "base-pci-bridge" 67 #define PCI_BRIDGE(obj) OBJECT_CHECK(PCIBridge, (obj), TYPE_PCI_BRIDGE) 68 69 struct PCIBridge { 70 /*< private >*/ 71 PCIDevice parent_obj; 72 /*< public >*/ 73 74 /* private member */ 75 PCIBus sec_bus; 76 /* 77 * Memory regions for the bridge's address spaces. These regions are not 78 * directly added to system_memory/system_io or its descendants. 79 * Bridge's secondary bus points to these, so that devices 80 * under the bridge see these regions as its address spaces. 81 * The regions are as large as the entire address space - 82 * they don't take into account any windows. 83 */ 84 MemoryRegion address_space_mem; 85 MemoryRegion address_space_io; 86 87 PCIBridgeWindows *windows; 88 89 pci_map_irq_fn map_irq; 90 const char *bus_name; 91 }; 92 93 #endif /* QEMU_PCI_BUS_H */ 94