1 /* 2 * Copyright (c) 2009 Laurent Vivier 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 #ifndef HW_MAC_DBDMA_H 23 #define HW_MAC_DBDMA_H 1 24 25 #include "exec/memory.h" 26 #include "qemu/iov.h" 27 #include "sysemu/dma.h" 28 29 typedef struct DBDMA_io DBDMA_io; 30 31 typedef void (*DBDMA_flush)(DBDMA_io *io); 32 typedef void (*DBDMA_rw)(DBDMA_io *io); 33 typedef void (*DBDMA_end)(DBDMA_io *io); 34 struct DBDMA_io { 35 void *opaque; 36 void *channel; 37 hwaddr addr; 38 int len; 39 int is_last; 40 int is_dma_out; 41 DBDMA_end dma_end; 42 /* DMA is in progress, don't start another one */ 43 bool processing; 44 /* unaligned last sector of a request */ 45 uint8_t head_remainder[0x200]; 46 uint8_t tail_remainder[0x200]; 47 QEMUIOVector iov; 48 /* DMA request */ 49 void *dma_mem; 50 dma_addr_t dma_len; 51 DMADirection dir; 52 }; 53 54 /* 55 * DBDMA control/status registers. All little-endian. 56 */ 57 58 #define DBDMA_CONTROL 0x00 59 #define DBDMA_STATUS 0x01 60 #define DBDMA_CMDPTR_HI 0x02 61 #define DBDMA_CMDPTR_LO 0x03 62 #define DBDMA_INTR_SEL 0x04 63 #define DBDMA_BRANCH_SEL 0x05 64 #define DBDMA_WAIT_SEL 0x06 65 #define DBDMA_XFER_MODE 0x07 66 #define DBDMA_DATA2PTR_HI 0x08 67 #define DBDMA_DATA2PTR_LO 0x09 68 #define DBDMA_RES1 0x0A 69 #define DBDMA_ADDRESS_HI 0x0B 70 #define DBDMA_BRANCH_ADDR_HI 0x0C 71 #define DBDMA_RES2 0x0D 72 #define DBDMA_RES3 0x0E 73 #define DBDMA_RES4 0x0F 74 75 #define DBDMA_REGS 16 76 #define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t)) 77 78 #define DBDMA_CHANNEL_SHIFT 7 79 #define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT) 80 81 #define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT) 82 83 /* Bits in control and status registers */ 84 85 #define RUN 0x8000 86 #define PAUSE 0x4000 87 #define FLUSH 0x2000 88 #define WAKE 0x1000 89 #define DEAD 0x0800 90 #define ACTIVE 0x0400 91 #define BT 0x0100 92 #define DEVSTAT 0x00ff 93 94 /* 95 * DBDMA command structure. These fields are all little-endian! 96 */ 97 98 typedef struct dbdma_cmd { 99 uint16_t req_count; /* requested byte transfer count */ 100 uint16_t command; /* command word (has bit-fields) */ 101 uint32_t phy_addr; /* physical data address */ 102 uint32_t cmd_dep; /* command-dependent field */ 103 uint16_t res_count; /* residual count after completion */ 104 uint16_t xfer_status; /* transfer status */ 105 } dbdma_cmd; 106 107 /* DBDMA command values in command field */ 108 109 #define COMMAND_MASK 0xf000 110 #define OUTPUT_MORE 0x0000 /* transfer memory data to stream */ 111 #define OUTPUT_LAST 0x1000 /* ditto followed by end marker */ 112 #define INPUT_MORE 0x2000 /* transfer stream data to memory */ 113 #define INPUT_LAST 0x3000 /* ditto, expect end marker */ 114 #define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */ 115 #define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */ 116 #define DBDMA_NOP 0x6000 /* do nothing */ 117 #define DBDMA_STOP 0x7000 /* suspend processing */ 118 119 /* Key values in command field */ 120 121 #define KEY_MASK 0x0700 122 #define KEY_STREAM0 0x0000 /* usual data stream */ 123 #define KEY_STREAM1 0x0100 /* control/status stream */ 124 #define KEY_STREAM2 0x0200 /* device-dependent stream */ 125 #define KEY_STREAM3 0x0300 /* device-dependent stream */ 126 #define KEY_STREAM4 0x0400 /* reserved */ 127 #define KEY_REGS 0x0500 /* device register space */ 128 #define KEY_SYSTEM 0x0600 /* system memory-mapped space */ 129 #define KEY_DEVICE 0x0700 /* device memory-mapped space */ 130 131 /* Interrupt control values in command field */ 132 133 #define INTR_MASK 0x0030 134 #define INTR_NEVER 0x0000 /* don't interrupt */ 135 #define INTR_IFSET 0x0010 /* intr if condition bit is 1 */ 136 #define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */ 137 #define INTR_ALWAYS 0x0030 /* always interrupt */ 138 139 /* Branch control values in command field */ 140 141 #define BR_MASK 0x000c 142 #define BR_NEVER 0x0000 /* don't branch */ 143 #define BR_IFSET 0x0004 /* branch if condition bit is 1 */ 144 #define BR_IFCLR 0x0008 /* branch if condition bit is 0 */ 145 #define BR_ALWAYS 0x000c /* always branch */ 146 147 /* Wait control values in command field */ 148 149 #define WAIT_MASK 0x0003 150 #define WAIT_NEVER 0x0000 /* don't wait */ 151 #define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */ 152 #define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */ 153 #define WAIT_ALWAYS 0x0003 /* always wait */ 154 155 typedef struct DBDMA_channel { 156 int channel; 157 uint32_t regs[DBDMA_REGS]; 158 qemu_irq irq; 159 DBDMA_io io; 160 DBDMA_rw rw; 161 DBDMA_flush flush; 162 dbdma_cmd current; 163 } DBDMA_channel; 164 165 typedef struct { 166 MemoryRegion mem; 167 DBDMA_channel channels[DBDMA_CHANNELS]; 168 QEMUBH *bh; 169 } DBDMAState; 170 171 /* Externally callable functions */ 172 173 void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq, 174 DBDMA_rw rw, DBDMA_flush flush, 175 void *opaque); 176 void DBDMA_kick(DBDMAState *dbdma); 177 void* DBDMA_init (MemoryRegion **dbdma_mem); 178 179 #endif 180