1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_H 21 #define PPC_PNV_H 22 23 #include "hw/boards.h" 24 #include "hw/sysbus.h" 25 #include "hw/ipmi/ipmi.h" 26 #include "hw/ppc/pnv_lpc.h" 27 #include "hw/ppc/pnv_pnor.h" 28 #include "hw/ppc/pnv_psi.h" 29 #include "hw/ppc/pnv_occ.h" 30 #include "hw/ppc/pnv_homer.h" 31 #include "hw/ppc/pnv_xive.h" 32 #include "hw/ppc/pnv_core.h" 33 #include "hw/pci-host/pnv_phb3.h" 34 #include "hw/pci-host/pnv_phb4.h" 35 #include "qom/object.h" 36 37 #define TYPE_PNV_CHIP "pnv-chip" 38 typedef struct PnvChip PnvChip; 39 typedef struct PnvChipClass PnvChipClass; 40 DECLARE_OBJ_CHECKERS(PnvChip, PnvChipClass, 41 PNV_CHIP, TYPE_PNV_CHIP) 42 43 struct PnvChip { 44 /*< private >*/ 45 SysBusDevice parent_obj; 46 47 /*< public >*/ 48 uint32_t chip_id; 49 uint64_t ram_start; 50 uint64_t ram_size; 51 52 uint32_t nr_cores; 53 uint32_t nr_threads; 54 uint64_t cores_mask; 55 PnvCore **cores; 56 57 uint32_t num_phbs; 58 59 MemoryRegion xscom_mmio; 60 MemoryRegion xscom; 61 AddressSpace xscom_as; 62 63 gchar *dt_isa_nodename; 64 }; 65 66 #define TYPE_PNV8_CHIP "pnv8-chip" 67 typedef struct Pnv8Chip Pnv8Chip; 68 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, 69 TYPE_PNV8_CHIP) 70 71 struct Pnv8Chip { 72 /*< private >*/ 73 PnvChip parent_obj; 74 75 /*< public >*/ 76 MemoryRegion icp_mmio; 77 78 PnvLpcController lpc; 79 Pnv8Psi psi; 80 PnvOCC occ; 81 PnvHomer homer; 82 83 #define PNV8_CHIP_PHB3_MAX 4 84 PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX]; 85 86 XICSFabric *xics; 87 }; 88 89 #define TYPE_PNV9_CHIP "pnv9-chip" 90 typedef struct Pnv9Chip Pnv9Chip; 91 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, 92 TYPE_PNV9_CHIP) 93 94 struct Pnv9Chip { 95 /*< private >*/ 96 PnvChip parent_obj; 97 98 /*< public >*/ 99 PnvXive xive; 100 Pnv9Psi psi; 101 PnvLpcController lpc; 102 PnvOCC occ; 103 PnvHomer homer; 104 105 uint32_t nr_quads; 106 PnvQuad *quads; 107 108 #define PNV9_CHIP_MAX_PEC 3 109 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; 110 }; 111 112 /* 113 * A SMT8 fused core is a pair of SMT4 cores. 114 */ 115 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 116 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 117 118 #define TYPE_PNV10_CHIP "pnv10-chip" 119 typedef struct Pnv10Chip Pnv10Chip; 120 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, 121 TYPE_PNV10_CHIP) 122 123 struct Pnv10Chip { 124 /*< private >*/ 125 PnvChip parent_obj; 126 127 /*< public >*/ 128 Pnv9Psi psi; 129 PnvLpcController lpc; 130 }; 131 132 struct PnvChipClass { 133 /*< private >*/ 134 SysBusDeviceClass parent_class; 135 136 /*< public >*/ 137 uint64_t chip_cfam_id; 138 uint64_t cores_mask; 139 uint32_t num_phbs; 140 141 DeviceRealize parent_realize; 142 143 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 144 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 145 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 146 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 147 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); 148 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 149 void (*dt_populate)(PnvChip *chip, void *fdt); 150 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 151 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 152 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 153 }; 154 155 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 156 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 157 158 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 159 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E, 160 TYPE_PNV_CHIP_POWER8E) 161 162 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 163 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, 164 TYPE_PNV_CHIP_POWER8) 165 166 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 167 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL, 168 TYPE_PNV_CHIP_POWER8NVL) 169 170 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 171 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, 172 TYPE_PNV_CHIP_POWER9) 173 174 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0") 175 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, 176 TYPE_PNV_CHIP_POWER10) 177 178 /* 179 * This generates a HW chip id depending on an index, as found on a 180 * two socket system with dual chip modules : 181 * 182 * 0x0, 0x1, 0x10, 0x11 183 * 184 * 4 chips should be the maximum 185 * 186 * TODO: use a machine property to define the chip ids 187 */ 188 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 189 190 /* 191 * Converts back a HW chip id to an index. This is useful to calculate 192 * the MMIO addresses of some controllers which depend on the chip id. 193 */ 194 #define PNV_CHIP_INDEX(chip) \ 195 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) 196 197 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); 198 199 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 200 typedef struct PnvMachineClass PnvMachineClass; 201 typedef struct PnvMachineState PnvMachineState; 202 DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass, 203 PNV_MACHINE, TYPE_PNV_MACHINE) 204 205 206 struct PnvMachineClass { 207 /*< private >*/ 208 MachineClass parent_class; 209 210 /*< public >*/ 211 const char *compat; 212 int compat_size; 213 214 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); 215 }; 216 217 struct PnvMachineState { 218 /*< private >*/ 219 MachineState parent_obj; 220 221 uint32_t initrd_base; 222 long initrd_size; 223 224 uint32_t num_chips; 225 PnvChip **chips; 226 227 ISABus *isa_bus; 228 uint32_t cpld_irqstate; 229 230 IPMIBmc *bmc; 231 Notifier powerdown_notifier; 232 233 PnvPnor *pnor; 234 235 hwaddr fw_load_addr; 236 }; 237 238 #define PNV_FDT_ADDR 0x01000000 239 #define PNV_TIMEBASE_FREQ 512000000ULL 240 241 /* 242 * BMC helpers 243 */ 244 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 245 void pnv_bmc_powerdown(IPMIBmc *bmc); 246 IPMIBmc *pnv_bmc_create(PnvPnor *pnor); 247 IPMIBmc *pnv_bmc_find(Error **errp); 248 void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); 249 250 /* 251 * POWER8 MMIO base addresses 252 */ 253 #define PNV_XSCOM_SIZE 0x800000000ull 254 #define PNV_XSCOM_BASE(chip) \ 255 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 256 257 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 258 #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull 259 #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ 260 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) 261 262 #define PNV_HOMER_SIZE 0x0000000000400000ull 263 #define PNV_HOMER_BASE(chip) \ 264 (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE) 265 266 267 /* 268 * XSCOM 0x20109CA defines the ICP BAR: 269 * 270 * 0:29 : bits 14 to 43 of address to define 1 MB region. 271 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 272 * 31:63 : Constant 0 273 * 274 * Usually defined as : 275 * 276 * 0xffffe00200000000 -> 0x0003ffff80000000 277 * 0xffffe00600000000 -> 0x0003ffff80100000 278 * 0xffffe02200000000 -> 0x0003ffff80800000 279 * 0xffffe02600000000 -> 0x0003ffff80900000 280 */ 281 #define PNV_ICP_SIZE 0x0000000000100000ull 282 #define PNV_ICP_BASE(chip) \ 283 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) 284 285 286 #define PNV_PSIHB_SIZE 0x0000000000100000ull 287 #define PNV_PSIHB_BASE(chip) \ 288 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) 289 290 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 291 #define PNV_PSIHB_FSP_BASE(chip) \ 292 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ 293 PNV_PSIHB_FSP_SIZE) 294 295 /* 296 * POWER9 MMIO base addresses 297 */ 298 #define PNV9_CHIP_BASE(chip, base) \ 299 ((base) + ((uint64_t) (chip)->chip_id << 42)) 300 301 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 302 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 303 304 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 305 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 306 307 #define PNV9_LPCM_SIZE 0x0000000100000000ull 308 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) 309 310 #define PNV9_PSIHB_SIZE 0x0000000000100000ull 311 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) 312 313 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 314 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 315 316 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 317 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 318 319 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull 320 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) 321 322 #define PNV9_XSCOM_SIZE 0x0000000400000000ull 323 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) 324 325 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 326 #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull 327 #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ 328 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) 329 330 #define PNV9_HOMER_SIZE 0x0000000000400000ull 331 #define PNV9_HOMER_BASE(chip) \ 332 (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) 333 334 /* 335 * POWER10 MMIO base addresses - 16TB stride per chip 336 */ 337 #define PNV10_CHIP_BASE(chip, base) \ 338 ((base) + ((uint64_t) (chip)->chip_id << 44)) 339 340 #define PNV10_XSCOM_SIZE 0x0000000400000000ull 341 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) 342 343 #define PNV10_LPCM_SIZE 0x0000000100000000ull 344 #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) 345 346 #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull 347 #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) 348 349 #define PNV10_PSIHB_SIZE 0x0000000000100000ull 350 #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) 351 352 #endif /* PPC_PNV_H */ 353