xref: /qemu/include/hw/ppc/pnv_nest_pervasive.h (revision 1adf2470) 
1*1adf2470SChalapathi V /*
2*1adf2470SChalapathi V  * QEMU PowerPC nest pervasive common chiplet model
3*1adf2470SChalapathi V  *
4*1adf2470SChalapathi V  * Copyright (c) 2023, IBM Corporation.
5*1adf2470SChalapathi V  *
6*1adf2470SChalapathi V  * SPDX-License-Identifier: GPL-2.0-or-later
7*1adf2470SChalapathi V  */
8*1adf2470SChalapathi V 
9*1adf2470SChalapathi V #ifndef PPC_PNV_NEST_CHIPLET_PERVASIVE_H
10*1adf2470SChalapathi V #define PPC_PNV_NEST_CHIPLET_PERVASIVE_H
11*1adf2470SChalapathi V 
12*1adf2470SChalapathi V #define TYPE_PNV_NEST_CHIPLET_PERVASIVE "pnv-nest-chiplet-pervasive"
13*1adf2470SChalapathi V #define PNV_NEST_CHIPLET_PERVASIVE(obj) OBJECT_CHECK(PnvNestChipletPervasive, (obj), TYPE_PNV_NEST_CHIPLET_PERVASIVE)
14*1adf2470SChalapathi V 
15*1adf2470SChalapathi V typedef struct PnvPervasiveCtrlRegs {
16*1adf2470SChalapathi V #define PNV_CPLT_CTRL_SIZE 6
17*1adf2470SChalapathi V     uint64_t cplt_ctrl[PNV_CPLT_CTRL_SIZE];
18*1adf2470SChalapathi V     uint64_t cplt_cfg0;
19*1adf2470SChalapathi V     uint64_t cplt_cfg1;
20*1adf2470SChalapathi V     uint64_t cplt_stat0;
21*1adf2470SChalapathi V     uint64_t cplt_mask0;
22*1adf2470SChalapathi V     uint64_t ctrl_protect_mode;
23*1adf2470SChalapathi V     uint64_t ctrl_atomic_lock;
24*1adf2470SChalapathi V } PnvPervasiveCtrlRegs;
25*1adf2470SChalapathi V 
26*1adf2470SChalapathi V typedef struct PnvNestChipletPervasive {
27*1adf2470SChalapathi V     DeviceState             parent;
28*1adf2470SChalapathi V     MemoryRegion            xscom_ctrl_regs_mr;
29*1adf2470SChalapathi V     PnvPervasiveCtrlRegs    control_regs;
30*1adf2470SChalapathi V } PnvNestChipletPervasive;
31*1adf2470SChalapathi V 
32*1adf2470SChalapathi V #endif /*PPC_PNV_NEST_CHIPLET_PERVASIVE_H */
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