1 /* 2 * QEMU PowerPC PowerNV Processor Service Interface (PSI) model 3 * 4 * Copyright (c) 2015-2017, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_PSI_H 21 #define PPC_PNV_PSI_H 22 23 #include "hw/sysbus.h" 24 #include "hw/ppc/xics.h" 25 #include "hw/ppc/xive.h" 26 #include "qom/object.h" 27 28 #define TYPE_PNV_PSI "pnv-psi" 29 typedef struct PnvPsi PnvPsi; 30 typedef struct PnvPsiClass PnvPsiClass; 31 DECLARE_OBJ_CHECKERS(PnvPsi, PnvPsiClass, 32 PNV_PSI, TYPE_PNV_PSI) 33 34 #define PSIHB_XSCOM_MAX 0x20 35 36 struct PnvPsi { 37 DeviceState parent; 38 39 MemoryRegion regs_mr; 40 uint64_t bar; 41 42 /* FSP region not supported */ 43 /* MemoryRegion fsp_mr; */ 44 uint64_t fsp_bar; 45 46 /* Interrupt generation */ 47 qemu_irq *qirqs; 48 49 /* Registers */ 50 uint64_t regs[PSIHB_XSCOM_MAX]; 51 52 MemoryRegion xscom_regs; 53 }; 54 55 #define TYPE_PNV8_PSI TYPE_PNV_PSI "-POWER8" 56 typedef struct Pnv8Psi Pnv8Psi; 57 DECLARE_INSTANCE_CHECKER(Pnv8Psi, PNV8_PSI, 58 TYPE_PNV8_PSI) 59 60 struct Pnv8Psi { 61 PnvPsi parent; 62 63 ICSState ics; 64 }; 65 66 #define TYPE_PNV9_PSI TYPE_PNV_PSI "-POWER9" 67 typedef struct Pnv9Psi Pnv9Psi; 68 DECLARE_INSTANCE_CHECKER(Pnv9Psi, PNV9_PSI, 69 TYPE_PNV9_PSI) 70 71 struct Pnv9Psi { 72 PnvPsi parent; 73 74 XiveSource source; 75 }; 76 77 #define TYPE_PNV10_PSI TYPE_PNV_PSI "-POWER10" 78 79 80 struct PnvPsiClass { 81 SysBusDeviceClass parent_class; 82 83 uint32_t xscom_pcba; 84 uint32_t xscom_size; 85 uint64_t bar_mask; 86 const char *compat; 87 int compat_size; 88 89 void (*irq_set)(PnvPsi *psi, int, bool state); 90 }; 91 92 /* The PSI and FSP interrupts are muxed on the same IRQ number */ 93 typedef enum PnvPsiIrq { 94 PSIHB_IRQ_PSI, /* internal use only */ 95 PSIHB_IRQ_FSP, /* internal use only */ 96 PSIHB_IRQ_OCC, 97 PSIHB_IRQ_FSI, 98 PSIHB_IRQ_LPC_I2C, 99 PSIHB_IRQ_LOCAL_ERR, 100 PSIHB_IRQ_EXTERNAL, 101 } PnvPsiIrq; 102 103 #define PSI_NUM_INTERRUPTS 6 104 105 void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state); 106 107 /* P9 PSI Interrupts */ 108 #define PSIHB9_IRQ_PSI 0 109 #define PSIHB9_IRQ_OCC 1 110 #define PSIHB9_IRQ_FSI 2 111 #define PSIHB9_IRQ_LPCHC 3 112 #define PSIHB9_IRQ_LOCAL_ERR 4 113 #define PSIHB9_IRQ_GLOBAL_ERR 5 114 #define PSIHB9_IRQ_TPM 6 115 #define PSIHB9_IRQ_LPC_SIRQ0 7 116 #define PSIHB9_IRQ_LPC_SIRQ1 8 117 #define PSIHB9_IRQ_LPC_SIRQ2 9 118 #define PSIHB9_IRQ_LPC_SIRQ3 10 119 #define PSIHB9_IRQ_SBE_I2C 11 120 #define PSIHB9_IRQ_DIO 12 121 #define PSIHB9_IRQ_PSU 13 122 #define PSIHB9_NUM_IRQS 14 123 124 void pnv_psi_pic_print_info(Pnv9Psi *psi, Monitor *mon); 125 126 #endif /* PPC_PNV_PSI_H */ 127