1 /* 2 * QEMU PowerPC PowerNV Processor Service Interface (PSI) model 3 * 4 * Copyright (c) 2015-2017, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_PSI_H 21 #define PPC_PNV_PSI_H 22 23 #include "hw/sysbus.h" 24 #include "hw/ppc/xics.h" 25 #include "hw/ppc/xive.h" 26 #include "qom/object.h" 27 28 #define TYPE_PNV_PSI "pnv-psi" 29 OBJECT_DECLARE_TYPE(PnvPsi, PnvPsiClass, 30 pnv_psi, PNV_PSI) 31 32 #define PSIHB_XSCOM_MAX 0x20 33 34 struct PnvPsi { 35 DeviceState parent; 36 37 MemoryRegion regs_mr; 38 uint64_t bar; 39 40 /* FSP region not supported */ 41 /* MemoryRegion fsp_mr; */ 42 uint64_t fsp_bar; 43 44 /* Interrupt generation */ 45 qemu_irq *qirqs; 46 47 /* Registers */ 48 uint64_t regs[PSIHB_XSCOM_MAX]; 49 50 MemoryRegion xscom_regs; 51 }; 52 53 #define TYPE_PNV8_PSI TYPE_PNV_PSI "-POWER8" 54 typedef struct Pnv8Psi Pnv8Psi; 55 DECLARE_INSTANCE_CHECKER(Pnv8Psi, PNV8_PSI, 56 TYPE_PNV8_PSI) 57 58 struct Pnv8Psi { 59 PnvPsi parent; 60 61 ICSState ics; 62 }; 63 64 #define TYPE_PNV9_PSI TYPE_PNV_PSI "-POWER9" 65 typedef struct Pnv9Psi Pnv9Psi; 66 DECLARE_INSTANCE_CHECKER(Pnv9Psi, PNV9_PSI, 67 TYPE_PNV9_PSI) 68 69 struct Pnv9Psi { 70 PnvPsi parent; 71 72 XiveSource source; 73 }; 74 75 #define TYPE_PNV10_PSI TYPE_PNV_PSI "-POWER10" 76 77 78 struct PnvPsiClass { 79 SysBusDeviceClass parent_class; 80 81 uint32_t xscom_pcba; 82 uint32_t xscom_size; 83 uint64_t bar_mask; 84 const char *compat; 85 int compat_size; 86 87 void (*irq_set)(PnvPsi *psi, int, bool state); 88 }; 89 90 /* The PSI and FSP interrupts are muxed on the same IRQ number */ 91 typedef enum PnvPsiIrq { 92 PSIHB_IRQ_PSI, /* internal use only */ 93 PSIHB_IRQ_FSP, /* internal use only */ 94 PSIHB_IRQ_OCC, 95 PSIHB_IRQ_FSI, 96 PSIHB_IRQ_LPC_I2C, 97 PSIHB_IRQ_LOCAL_ERR, 98 PSIHB_IRQ_EXTERNAL, 99 } PnvPsiIrq; 100 101 #define PSI_NUM_INTERRUPTS 6 102 103 void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state); 104 105 /* P9 PSI Interrupts */ 106 #define PSIHB9_IRQ_PSI 0 107 #define PSIHB9_IRQ_OCC 1 108 #define PSIHB9_IRQ_FSI 2 109 #define PSIHB9_IRQ_LPCHC 3 110 #define PSIHB9_IRQ_LOCAL_ERR 4 111 #define PSIHB9_IRQ_GLOBAL_ERR 5 112 #define PSIHB9_IRQ_TPM 6 113 #define PSIHB9_IRQ_LPC_SIRQ0 7 114 #define PSIHB9_IRQ_LPC_SIRQ1 8 115 #define PSIHB9_IRQ_LPC_SIRQ2 9 116 #define PSIHB9_IRQ_LPC_SIRQ3 10 117 #define PSIHB9_IRQ_SBE_I2C 11 118 #define PSIHB9_IRQ_DIO 12 119 #define PSIHB9_IRQ_PSU 13 120 #define PSIHB9_NUM_IRQS 14 121 122 void pnv_psi_pic_print_info(Pnv9Psi *psi, Monitor *mon); 123 124 #endif /* PPC_PNV_PSI_H */ 125