1 #if !defined(__HW_SPAPR_H__) 2 #define __HW_SPAPR_H__ 3 4 #include "sysemu/dma.h" 5 #include "hw/ppc/xics.h" 6 #include "hw/ppc/spapr_drc.h" 7 8 struct VIOsPAPRBus; 9 struct sPAPRPHBState; 10 struct sPAPRNVRAM; 11 typedef struct sPAPRConfigureConnectorState sPAPRConfigureConnectorState; 12 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 13 14 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 15 16 typedef struct sPAPREnvironment { 17 struct VIOsPAPRBus *vio_bus; 18 QLIST_HEAD(, sPAPRPHBState) phbs; 19 struct sPAPRNVRAM *nvram; 20 XICSState *icp; 21 DeviceState *rtc; 22 23 hwaddr ram_limit; 24 void *htab; 25 uint32_t htab_shift; 26 hwaddr rma_size; 27 int vrma_adjust; 28 hwaddr fdt_addr, rtas_addr; 29 ssize_t rtas_size; 30 void *rtas_blob; 31 void *fdt_skel; 32 target_ulong entry_point; 33 uint64_t rtc_offset; /* Now used only during incoming migration */ 34 struct PPCTimebase tb; 35 bool has_graphics; 36 37 uint32_t check_exception_irq; 38 Notifier epow_notifier; 39 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 40 41 /* Migration state */ 42 int htab_save_index; 43 bool htab_first_pass; 44 int htab_fd; 45 bool htab_fd_stale; 46 47 /* RTAS state */ 48 QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list; 49 } sPAPREnvironment; 50 51 #define H_SUCCESS 0 52 #define H_BUSY 1 /* Hardware busy -- retry later */ 53 #define H_CLOSED 2 /* Resource closed */ 54 #define H_NOT_AVAILABLE 3 55 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 56 #define H_PARTIAL 5 57 #define H_IN_PROGRESS 14 /* Kind of like busy */ 58 #define H_PAGE_REGISTERED 15 59 #define H_PARTIAL_STORE 16 60 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 61 #define H_CONTINUE 18 /* Returned from H_Join on success */ 62 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 63 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 64 is a good time to retry */ 65 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 66 is a good time to retry */ 67 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 68 is a good time to retry */ 69 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 70 is a good time to retry */ 71 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 72 is a good time to retry */ 73 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 74 is a good time to retry */ 75 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 76 #define H_HARDWARE -1 /* Hardware error */ 77 #define H_FUNCTION -2 /* Function not supported */ 78 #define H_PRIVILEGE -3 /* Caller not privileged */ 79 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 80 #define H_BAD_MODE -5 /* Illegal msr value */ 81 #define H_PTEG_FULL -6 /* PTEG is full */ 82 #define H_NOT_FOUND -7 /* PTE was not found" */ 83 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 84 #define H_NO_MEM -9 85 #define H_AUTHORITY -10 86 #define H_PERMISSION -11 87 #define H_DROPPED -12 88 #define H_SOURCE_PARM -13 89 #define H_DEST_PARM -14 90 #define H_REMOTE_PARM -15 91 #define H_RESOURCE -16 92 #define H_ADAPTER_PARM -17 93 #define H_RH_PARM -18 94 #define H_RCQ_PARM -19 95 #define H_SCQ_PARM -20 96 #define H_EQ_PARM -21 97 #define H_RT_PARM -22 98 #define H_ST_PARM -23 99 #define H_SIGT_PARM -24 100 #define H_TOKEN_PARM -25 101 #define H_MLENGTH_PARM -27 102 #define H_MEM_PARM -28 103 #define H_MEM_ACCESS_PARM -29 104 #define H_ATTR_PARM -30 105 #define H_PORT_PARM -31 106 #define H_MCG_PARM -32 107 #define H_VL_PARM -33 108 #define H_TSIZE_PARM -34 109 #define H_TRACE_PARM -35 110 111 #define H_MASK_PARM -37 112 #define H_MCG_FULL -38 113 #define H_ALIAS_EXIST -39 114 #define H_P_COUNTER -40 115 #define H_TABLE_FULL -41 116 #define H_ALT_TABLE -42 117 #define H_MR_CONDITION -43 118 #define H_NOT_ENOUGH_RESOURCES -44 119 #define H_R_STATE -45 120 #define H_RESCINDEND -46 121 #define H_P2 -55 122 #define H_P3 -56 123 #define H_P4 -57 124 #define H_P5 -58 125 #define H_P6 -59 126 #define H_P7 -60 127 #define H_P8 -61 128 #define H_P9 -62 129 #define H_UNSUPPORTED_FLAG -256 130 #define H_MULTI_THREADS_ACTIVE -9005 131 132 133 /* Long Busy is a condition that can be returned by the firmware 134 * when a call cannot be completed now, but the identical call 135 * should be retried later. This prevents calls blocking in the 136 * firmware for long periods of time. Annoyingly the firmware can return 137 * a range of return codes, hinting at how long we should wait before 138 * retrying. If you don't care for the hint, the macro below is a good 139 * way to check for the long_busy return codes 140 */ 141 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 142 && (x <= H_LONG_BUSY_END_RANGE)) 143 144 /* Flags */ 145 #define H_LARGE_PAGE (1ULL<<(63-16)) 146 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 147 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 148 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 149 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 150 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 151 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 152 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 153 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 154 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 155 #define H_ANDCOND (1ULL<<(63-33)) 156 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 157 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 158 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 159 #define H_COPY_PAGE (1ULL<<(63-49)) 160 #define H_N (1ULL<<(63-61)) 161 #define H_PP1 (1ULL<<(63-62)) 162 #define H_PP2 (1ULL<<(63-63)) 163 164 /* Values for 2nd argument to H_SET_MODE */ 165 #define H_SET_MODE_RESOURCE_SET_CIABR 1 166 #define H_SET_MODE_RESOURCE_SET_DAWR 2 167 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 168 #define H_SET_MODE_RESOURCE_LE 4 169 170 /* Flags for H_SET_MODE_RESOURCE_LE */ 171 #define H_SET_MODE_ENDIAN_BIG 0 172 #define H_SET_MODE_ENDIAN_LITTLE 1 173 174 /* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */ 175 #define H_SET_MODE_ADDR_TRANS_NONE 0 176 #define H_SET_MODE_ADDR_TRANS_0001_8000 2 177 #define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3 178 179 /* VASI States */ 180 #define H_VASI_INVALID 0 181 #define H_VASI_ENABLED 1 182 #define H_VASI_ABORTED 2 183 #define H_VASI_SUSPENDING 3 184 #define H_VASI_SUSPENDED 4 185 #define H_VASI_RESUMED 5 186 #define H_VASI_COMPLETED 6 187 188 /* DABRX flags */ 189 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 190 #define H_DABRX_KERNEL (1ULL<<(63-62)) 191 #define H_DABRX_USER (1ULL<<(63-63)) 192 193 /* Each control block has to be on a 4K boundary */ 194 #define H_CB_ALIGNMENT 4096 195 196 /* pSeries hypervisor opcodes */ 197 #define H_REMOVE 0x04 198 #define H_ENTER 0x08 199 #define H_READ 0x0c 200 #define H_CLEAR_MOD 0x10 201 #define H_CLEAR_REF 0x14 202 #define H_PROTECT 0x18 203 #define H_GET_TCE 0x1c 204 #define H_PUT_TCE 0x20 205 #define H_SET_SPRG0 0x24 206 #define H_SET_DABR 0x28 207 #define H_PAGE_INIT 0x2c 208 #define H_SET_ASR 0x30 209 #define H_ASR_ON 0x34 210 #define H_ASR_OFF 0x38 211 #define H_LOGICAL_CI_LOAD 0x3c 212 #define H_LOGICAL_CI_STORE 0x40 213 #define H_LOGICAL_CACHE_LOAD 0x44 214 #define H_LOGICAL_CACHE_STORE 0x48 215 #define H_LOGICAL_ICBI 0x4c 216 #define H_LOGICAL_DCBF 0x50 217 #define H_GET_TERM_CHAR 0x54 218 #define H_PUT_TERM_CHAR 0x58 219 #define H_REAL_TO_LOGICAL 0x5c 220 #define H_HYPERVISOR_DATA 0x60 221 #define H_EOI 0x64 222 #define H_CPPR 0x68 223 #define H_IPI 0x6c 224 #define H_IPOLL 0x70 225 #define H_XIRR 0x74 226 #define H_PERFMON 0x7c 227 #define H_MIGRATE_DMA 0x78 228 #define H_REGISTER_VPA 0xDC 229 #define H_CEDE 0xE0 230 #define H_CONFER 0xE4 231 #define H_PROD 0xE8 232 #define H_GET_PPP 0xEC 233 #define H_SET_PPP 0xF0 234 #define H_PURR 0xF4 235 #define H_PIC 0xF8 236 #define H_REG_CRQ 0xFC 237 #define H_FREE_CRQ 0x100 238 #define H_VIO_SIGNAL 0x104 239 #define H_SEND_CRQ 0x108 240 #define H_COPY_RDMA 0x110 241 #define H_REGISTER_LOGICAL_LAN 0x114 242 #define H_FREE_LOGICAL_LAN 0x118 243 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 244 #define H_SEND_LOGICAL_LAN 0x120 245 #define H_BULK_REMOVE 0x124 246 #define H_MULTICAST_CTRL 0x130 247 #define H_SET_XDABR 0x134 248 #define H_STUFF_TCE 0x138 249 #define H_PUT_TCE_INDIRECT 0x13C 250 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 251 #define H_VTERM_PARTNER_INFO 0x150 252 #define H_REGISTER_VTERM 0x154 253 #define H_FREE_VTERM 0x158 254 #define H_RESET_EVENTS 0x15C 255 #define H_ALLOC_RESOURCE 0x160 256 #define H_FREE_RESOURCE 0x164 257 #define H_MODIFY_QP 0x168 258 #define H_QUERY_QP 0x16C 259 #define H_REREGISTER_PMR 0x170 260 #define H_REGISTER_SMR 0x174 261 #define H_QUERY_MR 0x178 262 #define H_QUERY_MW 0x17C 263 #define H_QUERY_HCA 0x180 264 #define H_QUERY_PORT 0x184 265 #define H_MODIFY_PORT 0x188 266 #define H_DEFINE_AQP1 0x18C 267 #define H_GET_TRACE_BUFFER 0x190 268 #define H_DEFINE_AQP0 0x194 269 #define H_RESIZE_MR 0x198 270 #define H_ATTACH_MCQP 0x19C 271 #define H_DETACH_MCQP 0x1A0 272 #define H_CREATE_RPT 0x1A4 273 #define H_REMOVE_RPT 0x1A8 274 #define H_REGISTER_RPAGES 0x1AC 275 #define H_DISABLE_AND_GETC 0x1B0 276 #define H_ERROR_DATA 0x1B4 277 #define H_GET_HCA_INFO 0x1B8 278 #define H_GET_PERF_COUNT 0x1BC 279 #define H_MANAGE_TRACE 0x1C0 280 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 281 #define H_QUERY_INT_STATE 0x1E4 282 #define H_POLL_PENDING 0x1D8 283 #define H_ILLAN_ATTRIBUTES 0x244 284 #define H_MODIFY_HEA_QP 0x250 285 #define H_QUERY_HEA_QP 0x254 286 #define H_QUERY_HEA 0x258 287 #define H_QUERY_HEA_PORT 0x25C 288 #define H_MODIFY_HEA_PORT 0x260 289 #define H_REG_BCMC 0x264 290 #define H_DEREG_BCMC 0x268 291 #define H_REGISTER_HEA_RPAGES 0x26C 292 #define H_DISABLE_AND_GET_HEA 0x270 293 #define H_GET_HEA_INFO 0x274 294 #define H_ALLOC_HEA_RESOURCE 0x278 295 #define H_ADD_CONN 0x284 296 #define H_DEL_CONN 0x288 297 #define H_JOIN 0x298 298 #define H_VASI_STATE 0x2A4 299 #define H_ENABLE_CRQ 0x2B0 300 #define H_GET_EM_PARMS 0x2B8 301 #define H_SET_MPP 0x2D0 302 #define H_GET_MPP 0x2D4 303 #define H_XIRR_X 0x2FC 304 #define H_SET_MODE 0x31C 305 #define MAX_HCALL_OPCODE H_SET_MODE 306 307 /* The hcalls above are standardized in PAPR and implemented by pHyp 308 * as well. 309 * 310 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 311 * So far we just need one for H_RTAS, but in future we'll need more 312 * for extensions like virtio. We put those into the 0xf000-0xfffc 313 * range which is reserved by PAPR for "platform-specific" hcalls. 314 */ 315 #define KVMPPC_HCALL_BASE 0xf000 316 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 317 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 318 /* Client Architecture support */ 319 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 320 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS 321 322 extern sPAPREnvironment *spapr; 323 324 typedef struct sPAPRDeviceTreeUpdateHeader { 325 uint32_t version_id; 326 } sPAPRDeviceTreeUpdateHeader; 327 328 /*#define DEBUG_SPAPR_HCALLS*/ 329 330 #ifdef DEBUG_SPAPR_HCALLS 331 #define hcall_dprintf(fmt, ...) \ 332 do { fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); } while (0) 333 #else 334 #define hcall_dprintf(fmt, ...) \ 335 do { } while (0) 336 #endif 337 338 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr, 339 target_ulong opcode, 340 target_ulong *args); 341 342 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 343 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 344 target_ulong *args); 345 346 int spapr_allocate_irq(int hint, bool lsi); 347 int spapr_allocate_irq_block(int num, bool lsi, bool msi); 348 349 /* ibm,set-eeh-option */ 350 #define RTAS_EEH_DISABLE 0 351 #define RTAS_EEH_ENABLE 1 352 #define RTAS_EEH_THAW_IO 2 353 #define RTAS_EEH_THAW_DMA 3 354 355 /* ibm,get-config-addr-info2 */ 356 #define RTAS_GET_PE_ADDR 0 357 #define RTAS_GET_PE_MODE 1 358 #define RTAS_PE_MODE_NONE 0 359 #define RTAS_PE_MODE_NOT_SHARED 1 360 #define RTAS_PE_MODE_SHARED 2 361 362 /* ibm,read-slot-reset-state2 */ 363 #define RTAS_EEH_PE_STATE_NORMAL 0 364 #define RTAS_EEH_PE_STATE_RESET 1 365 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 366 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 367 #define RTAS_EEH_PE_STATE_UNAVAIL 5 368 #define RTAS_EEH_NOT_SUPPORT 0 369 #define RTAS_EEH_SUPPORT 1 370 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 371 #define RTAS_EEH_PE_RECOVER_INFO 0 372 373 /* ibm,set-slot-reset */ 374 #define RTAS_SLOT_RESET_DEACTIVATE 0 375 #define RTAS_SLOT_RESET_HOT 1 376 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 377 378 /* ibm,slot-error-detail */ 379 #define RTAS_SLOT_TEMP_ERR_LOG 1 380 #define RTAS_SLOT_PERM_ERR_LOG 2 381 382 /* RTAS return codes */ 383 #define RTAS_OUT_SUCCESS 0 384 #define RTAS_OUT_NO_ERRORS_FOUND 1 385 #define RTAS_OUT_HW_ERROR -1 386 #define RTAS_OUT_BUSY -2 387 #define RTAS_OUT_PARAM_ERROR -3 388 #define RTAS_OUT_NOT_SUPPORTED -3 389 #define RTAS_OUT_NOT_AUTHORIZED -9002 390 391 /* RTAS tokens */ 392 #define RTAS_TOKEN_BASE 0x2000 393 394 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 395 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 396 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 397 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 398 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 399 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 400 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 401 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 402 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 403 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 404 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 405 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 406 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 407 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 408 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 409 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 410 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 411 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 412 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 413 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 414 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 415 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 416 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 417 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 418 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 419 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 420 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 421 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 422 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 423 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 424 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 425 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 426 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 427 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 428 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 429 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 430 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 431 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 432 433 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x26) 434 435 /* RTAS ibm,get-system-parameter token values */ 436 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 437 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 438 #define RTAS_SYSPARM_UUID 48 439 440 /* RTAS indicator/sensor types 441 * 442 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 443 * 444 * NOTE: currently only DR-related sensors are implemented here 445 */ 446 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 447 #define RTAS_SENSOR_TYPE_DR 9002 448 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 449 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 450 451 /* Possible values for the platform-processor-diagnostics-run-mode parameter 452 * of the RTAS ibm,get-system-parameter call. 453 */ 454 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 455 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 456 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 457 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 458 459 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 460 { 461 return addr & ~0xF000000000000000ULL; 462 } 463 464 static inline uint32_t rtas_ld(target_ulong phys, int n) 465 { 466 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 467 } 468 469 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 470 { 471 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 472 } 473 474 static inline void rtas_st_buffer_direct(target_ulong phys, 475 target_ulong phys_len, 476 uint8_t *buffer, uint16_t buffer_len) 477 { 478 cpu_physical_memory_write(ppc64_phys_to_real(phys), buffer, 479 MIN(buffer_len, phys_len)); 480 } 481 482 static inline void rtas_st_buffer(target_ulong phys, target_ulong phys_len, 483 uint8_t *buffer, uint16_t buffer_len) 484 { 485 if (phys_len < 2) { 486 return; 487 } 488 stw_be_phys(&address_space_memory, 489 ppc64_phys_to_real(phys), buffer_len); 490 rtas_st_buffer_direct(phys + 2, phys_len - 2, buffer, buffer_len); 491 } 492 493 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr, 494 uint32_t token, 495 uint32_t nargs, target_ulong args, 496 uint32_t nret, target_ulong rets); 497 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 498 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPREnvironment *spapr, 499 uint32_t token, uint32_t nargs, target_ulong args, 500 uint32_t nret, target_ulong rets); 501 int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, 502 hwaddr rtas_size); 503 504 #define SPAPR_TCE_PAGE_SHIFT 12 505 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 506 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 507 508 #define SPAPR_VIO_BASE_LIOBN 0x00000000 509 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 510 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 511 (0x80000000 | ((phb_index) << 8) | (window_num)) 512 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 513 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 514 515 #define RTAS_ERROR_LOG_MAX 2048 516 517 #define RTAS_EVENT_SCAN_RATE 1 518 519 typedef struct sPAPRTCETable sPAPRTCETable; 520 521 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 522 #define SPAPR_TCE_TABLE(obj) \ 523 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 524 525 struct sPAPRTCETable { 526 DeviceState parent; 527 uint32_t liobn; 528 uint32_t nb_table; 529 uint64_t bus_offset; 530 uint32_t page_shift; 531 uint64_t *table; 532 bool bypass; 533 bool vfio_accel; 534 int fd; 535 MemoryRegion iommu; 536 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 537 QLIST_ENTRY(sPAPRTCETable) list; 538 }; 539 540 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 541 542 struct sPAPREventLogEntry { 543 int log_type; 544 bool exception; 545 void *data; 546 QTAILQ_ENTRY(sPAPREventLogEntry) next; 547 }; 548 549 void spapr_events_init(sPAPREnvironment *spapr); 550 void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq); 551 int spapr_h_cas_compose_response(target_ulong addr, target_ulong size); 552 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, 553 uint64_t bus_offset, 554 uint32_t page_shift, 555 uint32_t nb_table, 556 bool vfio_accel); 557 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 558 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 559 uint32_t liobn, uint64_t window, uint32_t size); 560 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 561 sPAPRTCETable *tcet); 562 void spapr_pci_switch_vga(bool big_endian); 563 void spapr_hotplug_req_add_event(sPAPRDRConnector *drc); 564 void spapr_hotplug_req_remove_event(sPAPRDRConnector *drc); 565 566 /* rtas-configure-connector state */ 567 struct sPAPRConfigureConnectorState { 568 uint32_t drc_index; 569 int fdt_offset; 570 int fdt_depth; 571 QTAILQ_ENTRY(sPAPRConfigureConnectorState) next; 572 }; 573 574 void spapr_ccs_reset_hook(void *opaque); 575 576 #define TYPE_SPAPR_RTC "spapr-rtc" 577 578 void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns); 579 int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset); 580 581 #endif /* !defined (__HW_SPAPR_H__) */ 582