1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 #include "hw/ppc/spapr_xive.h" /* For sPAPRXive */ 12 #include "hw/ppc/xics.h" /* For ICSState */ 13 14 struct VIOsPAPRBus; 15 struct sPAPRPHBState; 16 struct sPAPRNVRAM; 17 18 typedef struct sPAPREventLogEntry sPAPREventLogEntry; 19 typedef struct sPAPREventSource sPAPREventSource; 20 typedef struct sPAPRPendingHPT sPAPRPendingHPT; 21 22 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 23 #define SPAPR_ENTRY_POINT 0x100 24 25 #define SPAPR_TIMEBASE_FREQ 512000000ULL 26 27 #define TYPE_SPAPR_RTC "spapr-rtc" 28 29 #define SPAPR_RTC(obj) \ 30 OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC) 31 32 typedef struct sPAPRRTCState sPAPRRTCState; 33 struct sPAPRRTCState { 34 /*< private >*/ 35 DeviceState parent_obj; 36 int64_t ns_offset; 37 }; 38 39 typedef struct sPAPRDIMMState sPAPRDIMMState; 40 typedef struct sPAPRMachineClass sPAPRMachineClass; 41 42 #define TYPE_SPAPR_MACHINE "spapr-machine" 43 #define SPAPR_MACHINE(obj) \ 44 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 45 #define SPAPR_MACHINE_GET_CLASS(obj) \ 46 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE) 47 #define SPAPR_MACHINE_CLASS(klass) \ 48 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE) 49 50 typedef enum { 51 SPAPR_RESIZE_HPT_DEFAULT = 0, 52 SPAPR_RESIZE_HPT_DISABLED, 53 SPAPR_RESIZE_HPT_ENABLED, 54 SPAPR_RESIZE_HPT_REQUIRED, 55 } sPAPRResizeHPT; 56 57 /** 58 * Capabilities 59 */ 60 61 /* Hardware Transactional Memory */ 62 #define SPAPR_CAP_HTM 0x00 63 /* Vector Scalar Extensions */ 64 #define SPAPR_CAP_VSX 0x01 65 /* Decimal Floating Point */ 66 #define SPAPR_CAP_DFP 0x02 67 /* Cache Flush on Privilege Change */ 68 #define SPAPR_CAP_CFPC 0x03 69 /* Speculation Barrier Bounds Checking */ 70 #define SPAPR_CAP_SBBC 0x04 71 /* Indirect Branch Serialisation */ 72 #define SPAPR_CAP_IBS 0x05 73 /* HPT Maximum Page Size (encoded as a shift) */ 74 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 75 /* Nested KVM-HV */ 76 #define SPAPR_CAP_NESTED_KVM_HV 0x07 77 /* Large Decrementer */ 78 #define SPAPR_CAP_LARGE_DECREMENTER 0x08 79 /* Count Cache Flush Assist HW Instruction */ 80 #define SPAPR_CAP_CCF_ASSIST 0x09 81 /* Num Caps */ 82 #define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1) 83 84 /* 85 * Capability Values 86 */ 87 /* Bool Caps */ 88 #define SPAPR_CAP_OFF 0x00 89 #define SPAPR_CAP_ON 0x01 90 91 /* Custom Caps */ 92 93 /* Generic */ 94 #define SPAPR_CAP_BROKEN 0x00 95 #define SPAPR_CAP_WORKAROUND 0x01 96 #define SPAPR_CAP_FIXED 0x02 97 /* SPAPR_CAP_IBS (cap-ibs) */ 98 #define SPAPR_CAP_FIXED_IBS 0x02 99 #define SPAPR_CAP_FIXED_CCD 0x03 100 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 101 102 typedef struct sPAPRCapabilities sPAPRCapabilities; 103 struct sPAPRCapabilities { 104 uint8_t caps[SPAPR_CAP_NUM]; 105 }; 106 107 /** 108 * sPAPRMachineClass: 109 */ 110 struct sPAPRMachineClass { 111 /*< private >*/ 112 MachineClass parent_class; 113 114 /*< public >*/ 115 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 116 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 117 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 118 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 119 bool pre_2_10_has_unused_icps; 120 bool legacy_irq_allocation; 121 122 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, 123 uint64_t *buid, hwaddr *pio, 124 hwaddr *mmio32, hwaddr *mmio64, 125 unsigned n_dma, uint32_t *liobns, Error **errp); 126 sPAPRResizeHPT resize_hpt_default; 127 sPAPRCapabilities default_caps; 128 sPAPRIrq *irq; 129 }; 130 131 /** 132 * sPAPRMachineState: 133 */ 134 struct sPAPRMachineState { 135 /*< private >*/ 136 MachineState parent_obj; 137 138 struct VIOsPAPRBus *vio_bus; 139 QLIST_HEAD(, sPAPRPHBState) phbs; 140 struct sPAPRNVRAM *nvram; 141 ICSState *ics; 142 sPAPRRTCState rtc; 143 144 sPAPRResizeHPT resize_hpt; 145 void *htab; 146 uint32_t htab_shift; 147 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 148 sPAPRPendingHPT *pending_hpt; /* in-progress resize */ 149 150 hwaddr rma_size; 151 int vrma_adjust; 152 ssize_t rtas_size; 153 void *rtas_blob; 154 uint32_t fdt_size; 155 uint32_t fdt_initial_size; 156 void *fdt_blob; 157 long kernel_size; 158 bool kernel_le; 159 uint32_t initrd_base; 160 long initrd_size; 161 uint64_t rtc_offset; /* Now used only during incoming migration */ 162 struct PPCTimebase tb; 163 bool has_graphics; 164 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 165 166 Notifier epow_notifier; 167 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; 168 bool use_hotplug_event_source; 169 sPAPREventSource *event_sources; 170 171 /* ibm,client-architecture-support option negotiation */ 172 bool cas_reboot; 173 bool cas_legacy_guest_workaround; 174 sPAPROptionVector *ov5; /* QEMU-supported option vectors */ 175 sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 176 uint32_t max_compat_pvr; 177 178 /* Migration state */ 179 int htab_save_index; 180 bool htab_first_pass; 181 int htab_fd; 182 183 /* Pending DIMM unplug cache. It is populated when a LMB 184 * unplug starts. It can be regenerated if a migration 185 * occurs during the unplug process. */ 186 QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs; 187 188 /*< public >*/ 189 char *kvm_type; 190 char *host_model; 191 char *host_serial; 192 193 int32_t irq_map_nr; 194 unsigned long *irq_map; 195 sPAPRXive *xive; 196 sPAPRIrq *irq; 197 qemu_irq *qirqs; 198 199 bool cmd_line_caps[SPAPR_CAP_NUM]; 200 sPAPRCapabilities def, eff, mig; 201 }; 202 203 #define H_SUCCESS 0 204 #define H_BUSY 1 /* Hardware busy -- retry later */ 205 #define H_CLOSED 2 /* Resource closed */ 206 #define H_NOT_AVAILABLE 3 207 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 208 #define H_PARTIAL 5 209 #define H_IN_PROGRESS 14 /* Kind of like busy */ 210 #define H_PAGE_REGISTERED 15 211 #define H_PARTIAL_STORE 16 212 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 213 #define H_CONTINUE 18 /* Returned from H_Join on success */ 214 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 215 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 216 is a good time to retry */ 217 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 218 is a good time to retry */ 219 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 220 is a good time to retry */ 221 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 222 is a good time to retry */ 223 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 224 is a good time to retry */ 225 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 226 is a good time to retry */ 227 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 228 #define H_HARDWARE -1 /* Hardware error */ 229 #define H_FUNCTION -2 /* Function not supported */ 230 #define H_PRIVILEGE -3 /* Caller not privileged */ 231 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 232 #define H_BAD_MODE -5 /* Illegal msr value */ 233 #define H_PTEG_FULL -6 /* PTEG is full */ 234 #define H_NOT_FOUND -7 /* PTE was not found" */ 235 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 236 #define H_NO_MEM -9 237 #define H_AUTHORITY -10 238 #define H_PERMISSION -11 239 #define H_DROPPED -12 240 #define H_SOURCE_PARM -13 241 #define H_DEST_PARM -14 242 #define H_REMOTE_PARM -15 243 #define H_RESOURCE -16 244 #define H_ADAPTER_PARM -17 245 #define H_RH_PARM -18 246 #define H_RCQ_PARM -19 247 #define H_SCQ_PARM -20 248 #define H_EQ_PARM -21 249 #define H_RT_PARM -22 250 #define H_ST_PARM -23 251 #define H_SIGT_PARM -24 252 #define H_TOKEN_PARM -25 253 #define H_MLENGTH_PARM -27 254 #define H_MEM_PARM -28 255 #define H_MEM_ACCESS_PARM -29 256 #define H_ATTR_PARM -30 257 #define H_PORT_PARM -31 258 #define H_MCG_PARM -32 259 #define H_VL_PARM -33 260 #define H_TSIZE_PARM -34 261 #define H_TRACE_PARM -35 262 263 #define H_MASK_PARM -37 264 #define H_MCG_FULL -38 265 #define H_ALIAS_EXIST -39 266 #define H_P_COUNTER -40 267 #define H_TABLE_FULL -41 268 #define H_ALT_TABLE -42 269 #define H_MR_CONDITION -43 270 #define H_NOT_ENOUGH_RESOURCES -44 271 #define H_R_STATE -45 272 #define H_RESCINDEND -46 273 #define H_P2 -55 274 #define H_P3 -56 275 #define H_P4 -57 276 #define H_P5 -58 277 #define H_P6 -59 278 #define H_P7 -60 279 #define H_P8 -61 280 #define H_P9 -62 281 #define H_UNSUPPORTED_FLAG -256 282 #define H_MULTI_THREADS_ACTIVE -9005 283 284 285 /* Long Busy is a condition that can be returned by the firmware 286 * when a call cannot be completed now, but the identical call 287 * should be retried later. This prevents calls blocking in the 288 * firmware for long periods of time. Annoyingly the firmware can return 289 * a range of return codes, hinting at how long we should wait before 290 * retrying. If you don't care for the hint, the macro below is a good 291 * way to check for the long_busy return codes 292 */ 293 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 294 && (x <= H_LONG_BUSY_END_RANGE)) 295 296 /* Flags */ 297 #define H_LARGE_PAGE (1ULL<<(63-16)) 298 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 299 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 300 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 301 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 302 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 303 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 304 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 305 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 306 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 307 #define H_ANDCOND (1ULL<<(63-33)) 308 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 309 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 310 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 311 #define H_COPY_PAGE (1ULL<<(63-49)) 312 #define H_N (1ULL<<(63-61)) 313 #define H_PP1 (1ULL<<(63-62)) 314 #define H_PP2 (1ULL<<(63-63)) 315 316 /* Values for 2nd argument to H_SET_MODE */ 317 #define H_SET_MODE_RESOURCE_SET_CIABR 1 318 #define H_SET_MODE_RESOURCE_SET_DAWR 2 319 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 320 #define H_SET_MODE_RESOURCE_LE 4 321 322 /* Flags for H_SET_MODE_RESOURCE_LE */ 323 #define H_SET_MODE_ENDIAN_BIG 0 324 #define H_SET_MODE_ENDIAN_LITTLE 1 325 326 /* VASI States */ 327 #define H_VASI_INVALID 0 328 #define H_VASI_ENABLED 1 329 #define H_VASI_ABORTED 2 330 #define H_VASI_SUSPENDING 3 331 #define H_VASI_SUSPENDED 4 332 #define H_VASI_RESUMED 5 333 #define H_VASI_COMPLETED 6 334 335 /* DABRX flags */ 336 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 337 #define H_DABRX_KERNEL (1ULL<<(63-62)) 338 #define H_DABRX_USER (1ULL<<(63-63)) 339 340 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 341 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 342 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 343 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 344 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 345 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 346 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 347 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 348 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 349 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 350 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 351 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 352 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 353 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 354 355 /* Each control block has to be on a 4K boundary */ 356 #define H_CB_ALIGNMENT 4096 357 358 /* pSeries hypervisor opcodes */ 359 #define H_REMOVE 0x04 360 #define H_ENTER 0x08 361 #define H_READ 0x0c 362 #define H_CLEAR_MOD 0x10 363 #define H_CLEAR_REF 0x14 364 #define H_PROTECT 0x18 365 #define H_GET_TCE 0x1c 366 #define H_PUT_TCE 0x20 367 #define H_SET_SPRG0 0x24 368 #define H_SET_DABR 0x28 369 #define H_PAGE_INIT 0x2c 370 #define H_SET_ASR 0x30 371 #define H_ASR_ON 0x34 372 #define H_ASR_OFF 0x38 373 #define H_LOGICAL_CI_LOAD 0x3c 374 #define H_LOGICAL_CI_STORE 0x40 375 #define H_LOGICAL_CACHE_LOAD 0x44 376 #define H_LOGICAL_CACHE_STORE 0x48 377 #define H_LOGICAL_ICBI 0x4c 378 #define H_LOGICAL_DCBF 0x50 379 #define H_GET_TERM_CHAR 0x54 380 #define H_PUT_TERM_CHAR 0x58 381 #define H_REAL_TO_LOGICAL 0x5c 382 #define H_HYPERVISOR_DATA 0x60 383 #define H_EOI 0x64 384 #define H_CPPR 0x68 385 #define H_IPI 0x6c 386 #define H_IPOLL 0x70 387 #define H_XIRR 0x74 388 #define H_PERFMON 0x7c 389 #define H_MIGRATE_DMA 0x78 390 #define H_REGISTER_VPA 0xDC 391 #define H_CEDE 0xE0 392 #define H_CONFER 0xE4 393 #define H_PROD 0xE8 394 #define H_GET_PPP 0xEC 395 #define H_SET_PPP 0xF0 396 #define H_PURR 0xF4 397 #define H_PIC 0xF8 398 #define H_REG_CRQ 0xFC 399 #define H_FREE_CRQ 0x100 400 #define H_VIO_SIGNAL 0x104 401 #define H_SEND_CRQ 0x108 402 #define H_COPY_RDMA 0x110 403 #define H_REGISTER_LOGICAL_LAN 0x114 404 #define H_FREE_LOGICAL_LAN 0x118 405 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 406 #define H_SEND_LOGICAL_LAN 0x120 407 #define H_BULK_REMOVE 0x124 408 #define H_MULTICAST_CTRL 0x130 409 #define H_SET_XDABR 0x134 410 #define H_STUFF_TCE 0x138 411 #define H_PUT_TCE_INDIRECT 0x13C 412 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 413 #define H_VTERM_PARTNER_INFO 0x150 414 #define H_REGISTER_VTERM 0x154 415 #define H_FREE_VTERM 0x158 416 #define H_RESET_EVENTS 0x15C 417 #define H_ALLOC_RESOURCE 0x160 418 #define H_FREE_RESOURCE 0x164 419 #define H_MODIFY_QP 0x168 420 #define H_QUERY_QP 0x16C 421 #define H_REREGISTER_PMR 0x170 422 #define H_REGISTER_SMR 0x174 423 #define H_QUERY_MR 0x178 424 #define H_QUERY_MW 0x17C 425 #define H_QUERY_HCA 0x180 426 #define H_QUERY_PORT 0x184 427 #define H_MODIFY_PORT 0x188 428 #define H_DEFINE_AQP1 0x18C 429 #define H_GET_TRACE_BUFFER 0x190 430 #define H_DEFINE_AQP0 0x194 431 #define H_RESIZE_MR 0x198 432 #define H_ATTACH_MCQP 0x19C 433 #define H_DETACH_MCQP 0x1A0 434 #define H_CREATE_RPT 0x1A4 435 #define H_REMOVE_RPT 0x1A8 436 #define H_REGISTER_RPAGES 0x1AC 437 #define H_DISABLE_AND_GETC 0x1B0 438 #define H_ERROR_DATA 0x1B4 439 #define H_GET_HCA_INFO 0x1B8 440 #define H_GET_PERF_COUNT 0x1BC 441 #define H_MANAGE_TRACE 0x1C0 442 #define H_GET_CPU_CHARACTERISTICS 0x1C8 443 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 444 #define H_QUERY_INT_STATE 0x1E4 445 #define H_POLL_PENDING 0x1D8 446 #define H_ILLAN_ATTRIBUTES 0x244 447 #define H_MODIFY_HEA_QP 0x250 448 #define H_QUERY_HEA_QP 0x254 449 #define H_QUERY_HEA 0x258 450 #define H_QUERY_HEA_PORT 0x25C 451 #define H_MODIFY_HEA_PORT 0x260 452 #define H_REG_BCMC 0x264 453 #define H_DEREG_BCMC 0x268 454 #define H_REGISTER_HEA_RPAGES 0x26C 455 #define H_DISABLE_AND_GET_HEA 0x270 456 #define H_GET_HEA_INFO 0x274 457 #define H_ALLOC_HEA_RESOURCE 0x278 458 #define H_ADD_CONN 0x284 459 #define H_DEL_CONN 0x288 460 #define H_JOIN 0x298 461 #define H_VASI_STATE 0x2A4 462 #define H_ENABLE_CRQ 0x2B0 463 #define H_GET_EM_PARMS 0x2B8 464 #define H_SET_MPP 0x2D0 465 #define H_GET_MPP 0x2D4 466 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 467 #define H_XIRR_X 0x2FC 468 #define H_RANDOM 0x300 469 #define H_SET_MODE 0x31C 470 #define H_RESIZE_HPT_PREPARE 0x36C 471 #define H_RESIZE_HPT_COMMIT 0x370 472 #define H_CLEAN_SLB 0x374 473 #define H_INVALIDATE_PID 0x378 474 #define H_REGISTER_PROC_TBL 0x37C 475 #define H_SIGNAL_SYS_RESET 0x380 476 477 #define H_INT_GET_SOURCE_INFO 0x3A8 478 #define H_INT_SET_SOURCE_CONFIG 0x3AC 479 #define H_INT_GET_SOURCE_CONFIG 0x3B0 480 #define H_INT_GET_QUEUE_INFO 0x3B4 481 #define H_INT_SET_QUEUE_CONFIG 0x3B8 482 #define H_INT_GET_QUEUE_CONFIG 0x3BC 483 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 484 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 485 #define H_INT_ESB 0x3C8 486 #define H_INT_SYNC 0x3CC 487 #define H_INT_RESET 0x3D0 488 489 #define MAX_HCALL_OPCODE H_INT_RESET 490 491 /* The hcalls above are standardized in PAPR and implemented by pHyp 492 * as well. 493 * 494 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 495 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 496 * for "platform-specific" hcalls. 497 */ 498 #define KVMPPC_HCALL_BASE 0xf000 499 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 500 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 501 /* Client Architecture support */ 502 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 503 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 504 #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT 505 506 typedef struct sPAPRDeviceTreeUpdateHeader { 507 uint32_t version_id; 508 } sPAPRDeviceTreeUpdateHeader; 509 510 #define hcall_dprintf(fmt, ...) \ 511 do { \ 512 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 513 } while (0) 514 515 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 516 target_ulong opcode, 517 target_ulong *args); 518 519 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 520 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 521 target_ulong *args); 522 523 /* ibm,set-eeh-option */ 524 #define RTAS_EEH_DISABLE 0 525 #define RTAS_EEH_ENABLE 1 526 #define RTAS_EEH_THAW_IO 2 527 #define RTAS_EEH_THAW_DMA 3 528 529 /* ibm,get-config-addr-info2 */ 530 #define RTAS_GET_PE_ADDR 0 531 #define RTAS_GET_PE_MODE 1 532 #define RTAS_PE_MODE_NONE 0 533 #define RTAS_PE_MODE_NOT_SHARED 1 534 #define RTAS_PE_MODE_SHARED 2 535 536 /* ibm,read-slot-reset-state2 */ 537 #define RTAS_EEH_PE_STATE_NORMAL 0 538 #define RTAS_EEH_PE_STATE_RESET 1 539 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 540 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 541 #define RTAS_EEH_PE_STATE_UNAVAIL 5 542 #define RTAS_EEH_NOT_SUPPORT 0 543 #define RTAS_EEH_SUPPORT 1 544 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 545 #define RTAS_EEH_PE_RECOVER_INFO 0 546 547 /* ibm,set-slot-reset */ 548 #define RTAS_SLOT_RESET_DEACTIVATE 0 549 #define RTAS_SLOT_RESET_HOT 1 550 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 551 552 /* ibm,slot-error-detail */ 553 #define RTAS_SLOT_TEMP_ERR_LOG 1 554 #define RTAS_SLOT_PERM_ERR_LOG 2 555 556 /* RTAS return codes */ 557 #define RTAS_OUT_SUCCESS 0 558 #define RTAS_OUT_NO_ERRORS_FOUND 1 559 #define RTAS_OUT_HW_ERROR -1 560 #define RTAS_OUT_BUSY -2 561 #define RTAS_OUT_PARAM_ERROR -3 562 #define RTAS_OUT_NOT_SUPPORTED -3 563 #define RTAS_OUT_NO_SUCH_INDICATOR -3 564 #define RTAS_OUT_NOT_AUTHORIZED -9002 565 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 566 567 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 568 #define RTAS_DDW_PGSIZE_4K 0x01 569 #define RTAS_DDW_PGSIZE_64K 0x02 570 #define RTAS_DDW_PGSIZE_16M 0x04 571 #define RTAS_DDW_PGSIZE_32M 0x08 572 #define RTAS_DDW_PGSIZE_64M 0x10 573 #define RTAS_DDW_PGSIZE_128M 0x20 574 #define RTAS_DDW_PGSIZE_256M 0x40 575 #define RTAS_DDW_PGSIZE_16G 0x80 576 577 /* RTAS tokens */ 578 #define RTAS_TOKEN_BASE 0x2000 579 580 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 581 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 582 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 583 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 584 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 585 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 586 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 587 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 588 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 589 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 590 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 591 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 592 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 593 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 594 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 595 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 596 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 597 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 598 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 599 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 600 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 601 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 602 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 603 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 604 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 605 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 606 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 607 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 608 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 609 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 610 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 611 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 612 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 613 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 614 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 615 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 616 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 617 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 618 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 619 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 620 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 621 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 622 623 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) 624 625 /* RTAS ibm,get-system-parameter token values */ 626 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 627 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 628 #define RTAS_SYSPARM_UUID 48 629 630 /* RTAS indicator/sensor types 631 * 632 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 633 * 634 * NOTE: currently only DR-related sensors are implemented here 635 */ 636 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 637 #define RTAS_SENSOR_TYPE_DR 9002 638 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 639 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 640 641 /* Possible values for the platform-processor-diagnostics-run-mode parameter 642 * of the RTAS ibm,get-system-parameter call. 643 */ 644 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 645 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 646 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 647 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 648 649 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 650 { 651 return addr & ~0xF000000000000000ULL; 652 } 653 654 static inline uint32_t rtas_ld(target_ulong phys, int n) 655 { 656 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 657 } 658 659 static inline uint64_t rtas_ldq(target_ulong phys, int n) 660 { 661 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 662 } 663 664 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 665 { 666 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 667 } 668 669 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm, 670 uint32_t token, 671 uint32_t nargs, target_ulong args, 672 uint32_t nret, target_ulong rets); 673 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 674 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm, 675 uint32_t token, uint32_t nargs, target_ulong args, 676 uint32_t nret, target_ulong rets); 677 void spapr_dt_rtas_tokens(void *fdt, int rtas); 678 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); 679 680 #define SPAPR_TCE_PAGE_SHIFT 12 681 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 682 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 683 684 #define SPAPR_VIO_BASE_LIOBN 0x00000000 685 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 686 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 687 (0x80000000 | ((phb_index) << 8) | (window_num)) 688 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 689 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 690 691 #define RTAS_ERROR_LOG_MAX 2048 692 693 #define RTAS_EVENT_SCAN_RATE 1 694 695 /* This helper should be used to encode interrupt specifiers when the related 696 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 697 * VIO devices, RTAS event sources and PHBs). 698 */ 699 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 700 { 701 intspec[0] = cpu_to_be32(irq); 702 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 703 } 704 705 typedef struct sPAPRTCETable sPAPRTCETable; 706 707 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 708 #define SPAPR_TCE_TABLE(obj) \ 709 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) 710 711 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 712 #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 713 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 714 715 struct sPAPRTCETable { 716 DeviceState parent; 717 uint32_t liobn; 718 uint32_t nb_table; 719 uint64_t bus_offset; 720 uint32_t page_shift; 721 uint64_t *table; 722 uint32_t mig_nb_table; 723 uint64_t *mig_table; 724 bool bypass; 725 bool need_vfio; 726 int fd; 727 MemoryRegion root; 728 IOMMUMemoryRegion iommu; 729 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */ 730 QLIST_ENTRY(sPAPRTCETable) list; 731 }; 732 733 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn); 734 735 struct sPAPREventLogEntry { 736 uint32_t summary; 737 uint32_t extended_length; 738 void *extended_log; 739 QTAILQ_ENTRY(sPAPREventLogEntry) next; 740 }; 741 742 void spapr_events_init(sPAPRMachineState *sm); 743 void spapr_dt_events(sPAPRMachineState *sm, void *fdt); 744 int spapr_h_cas_compose_response(sPAPRMachineState *sm, 745 target_ulong addr, target_ulong size, 746 sPAPROptionVector *ov5_updates); 747 void close_htab_fd(sPAPRMachineState *spapr); 748 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr); 749 void spapr_free_hpt(sPAPRMachineState *spapr); 750 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 751 void spapr_tce_table_enable(sPAPRTCETable *tcet, 752 uint32_t page_shift, uint64_t bus_offset, 753 uint32_t nb_table); 754 void spapr_tce_table_disable(sPAPRTCETable *tcet); 755 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio); 756 757 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); 758 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 759 uint32_t liobn, uint64_t window, uint32_t size); 760 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 761 sPAPRTCETable *tcet); 762 void spapr_pci_switch_vga(bool big_endian); 763 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc); 764 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc); 765 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type, 766 uint32_t count); 767 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type, 768 uint32_t count); 769 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type, 770 uint32_t count, uint32_t index); 771 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type, 772 uint32_t count, uint32_t index); 773 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 774 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 775 Error **errp); 776 void spapr_clear_pending_events(sPAPRMachineState *spapr); 777 int spapr_max_server_number(sPAPRMachineState *spapr); 778 779 /* DRC callbacks. */ 780 void spapr_core_release(DeviceState *dev); 781 int spapr_core_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr, 782 void *fdt, int *fdt_start_offset, Error **errp); 783 void spapr_lmb_release(DeviceState *dev); 784 int spapr_lmb_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr, 785 void *fdt, int *fdt_start_offset, Error **errp); 786 void spapr_phb_release(DeviceState *dev); 787 int spapr_phb_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr, 788 void *fdt, int *fdt_start_offset, Error **errp); 789 790 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns); 791 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset); 792 793 #define TYPE_SPAPR_RNG "spapr-rng" 794 795 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */ 796 797 /* 798 * This defines the maximum number of DIMM slots we can have for sPAPR 799 * guest. This is not defined by sPAPR but we are defining it to 32 slots 800 * based on default number of slots provided by PowerPC kernel. 801 */ 802 #define SPAPR_MAX_RAM_SLOTS 32 803 804 /* 1GB alignment for hotplug memory region */ 805 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 806 807 /* 808 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 809 * property under ibm,dynamic-reconfiguration-memory node. 810 */ 811 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 812 813 /* 814 * Defines for flag value in ibm,dynamic-memory property under 815 * ibm,dynamic-reconfiguration-memory node. 816 */ 817 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 818 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 819 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 820 821 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 822 823 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 824 825 int spapr_get_vcpu_id(PowerPCCPU *cpu); 826 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 827 PowerPCCPU *spapr_find_cpu(int vcpu_id); 828 829 int spapr_caps_pre_load(void *opaque); 830 int spapr_caps_pre_save(void *opaque); 831 832 /* 833 * Handling of optional capabilities 834 */ 835 extern const VMStateDescription vmstate_spapr_cap_htm; 836 extern const VMStateDescription vmstate_spapr_cap_vsx; 837 extern const VMStateDescription vmstate_spapr_cap_dfp; 838 extern const VMStateDescription vmstate_spapr_cap_cfpc; 839 extern const VMStateDescription vmstate_spapr_cap_sbbc; 840 extern const VMStateDescription vmstate_spapr_cap_ibs; 841 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 842 extern const VMStateDescription vmstate_spapr_cap_large_decr; 843 extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 844 845 static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap) 846 { 847 return spapr->eff.caps[cap]; 848 } 849 850 void spapr_caps_init(sPAPRMachineState *spapr); 851 void spapr_caps_apply(sPAPRMachineState *spapr); 852 void spapr_caps_cpu_apply(sPAPRMachineState *spapr, PowerPCCPU *cpu); 853 void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp); 854 int spapr_caps_post_migration(sPAPRMachineState *spapr); 855 856 void spapr_check_pagesize(sPAPRMachineState *spapr, hwaddr pagesize, 857 Error **errp); 858 /* 859 * XIVE definitions 860 */ 861 #define SPAPR_OV5_XIVE_LEGACY 0x0 862 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 863 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 864 865 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 866 #endif /* HW_SPAPR_H */ 867