1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics 5 * 6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 28 #ifndef XICS_H 29 #define XICS_H 30 31 #include "exec/memory.h" 32 #include "hw/qdev-core.h" 33 #include "qom/object.h" 34 35 #define XICS_IPI 0x2 36 #define XICS_BUID 0x1 37 #define XICS_IRQ_BASE (XICS_BUID << 12) 38 39 /* 40 * We currently only support one BUID which is our interrupt base 41 * (the kernel implementation supports more but we don't exploit 42 * that yet) 43 */ 44 typedef struct ICPStateClass ICPStateClass; 45 typedef struct ICPState ICPState; 46 typedef struct PnvICPState PnvICPState; 47 typedef struct ICSStateClass ICSStateClass; 48 typedef struct ICSState ICSState; 49 typedef struct ICSIRQState ICSIRQState; 50 typedef struct XICSFabric XICSFabric; 51 52 #define TYPE_ICP "icp" 53 DECLARE_OBJ_CHECKERS(ICPState, ICPStateClass, 54 ICP, TYPE_ICP) 55 56 #define TYPE_PNV_ICP "pnv-icp" 57 DECLARE_INSTANCE_CHECKER(PnvICPState, PNV_ICP, 58 TYPE_PNV_ICP) 59 60 61 struct ICPStateClass { 62 DeviceClass parent_class; 63 64 DeviceRealize parent_realize; 65 }; 66 67 struct ICPState { 68 /*< private >*/ 69 DeviceState parent_obj; 70 /*< public >*/ 71 CPUState *cs; 72 ICSState *xirr_owner; 73 uint32_t xirr; 74 uint8_t pending_priority; 75 uint8_t mfrr; 76 qemu_irq output; 77 78 XICSFabric *xics; 79 }; 80 81 #define ICP_PROP_XICS "xics" 82 #define ICP_PROP_CPU "cpu" 83 84 struct PnvICPState { 85 ICPState parent_obj; 86 87 MemoryRegion mmio; 88 uint32_t links[3]; 89 }; 90 91 #define TYPE_ICS "ics" 92 DECLARE_OBJ_CHECKERS(ICSState, ICSStateClass, 93 ICS, TYPE_ICS) 94 95 96 struct ICSStateClass { 97 DeviceClass parent_class; 98 99 DeviceRealize parent_realize; 100 DeviceReset parent_reset; 101 102 void (*reject)(ICSState *s, uint32_t irq); 103 void (*resend)(ICSState *s); 104 }; 105 106 struct ICSState { 107 /*< private >*/ 108 DeviceState parent_obj; 109 /*< public >*/ 110 uint32_t nr_irqs; 111 uint32_t offset; 112 ICSIRQState *irqs; 113 XICSFabric *xics; 114 }; 115 116 #define ICS_PROP_XICS "xics" 117 118 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr) 119 { 120 return (nr >= ics->offset) && (nr < (ics->offset + ics->nr_irqs)); 121 } 122 123 struct ICSIRQState { 124 uint32_t server; 125 uint8_t priority; 126 uint8_t saved_priority; 127 #define XICS_STATUS_ASSERTED 0x1 128 #define XICS_STATUS_SENT 0x2 129 #define XICS_STATUS_REJECTED 0x4 130 #define XICS_STATUS_MASKED_PENDING 0x8 131 #define XICS_STATUS_PRESENTED 0x10 132 #define XICS_STATUS_QUEUED 0x20 133 uint8_t status; 134 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */ 135 #define XICS_FLAGS_IRQ_LSI 0x1 136 #define XICS_FLAGS_IRQ_MSI 0x2 137 #define XICS_FLAGS_IRQ_MASK 0x3 138 uint8_t flags; 139 }; 140 141 #define TYPE_XICS_FABRIC "xics-fabric" 142 #define XICS_FABRIC(obj) \ 143 INTERFACE_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC) 144 typedef struct XICSFabricClass XICSFabricClass; 145 DECLARE_CLASS_CHECKERS(XICSFabricClass, XICS_FABRIC, 146 TYPE_XICS_FABRIC) 147 148 struct XICSFabricClass { 149 InterfaceClass parent; 150 ICSState *(*ics_get)(XICSFabric *xi, int irq); 151 void (*ics_resend)(XICSFabric *xi); 152 ICPState *(*icp_get)(XICSFabric *xi, int server); 153 }; 154 155 ICPState *xics_icp_get(XICSFabric *xi, int server); 156 157 /* Internal XICS interfaces */ 158 void icp_set_cppr(ICPState *icp, uint8_t cppr); 159 void icp_set_mfrr(ICPState *icp, uint8_t mfrr); 160 uint32_t icp_accept(ICPState *ss); 161 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr); 162 void icp_eoi(ICPState *icp, uint32_t xirr); 163 void icp_irq(ICSState *ics, int server, int nr, uint8_t priority); 164 void icp_reset(ICPState *icp); 165 166 void ics_write_xive(ICSState *ics, int nr, int server, 167 uint8_t priority, uint8_t saved_priority); 168 void ics_set_irq(void *opaque, int srcno, int val); 169 170 static inline bool ics_irq_free(ICSState *ics, uint32_t srcno) 171 { 172 return !(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK); 173 } 174 175 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi); 176 void icp_pic_print_info(ICPState *icp, Monitor *mon); 177 void ics_pic_print_info(ICSState *ics, Monitor *mon); 178 179 void ics_resend(ICSState *ics); 180 void icp_resend(ICPState *ss); 181 182 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, 183 Error **errp); 184 void icp_destroy(ICPState *icp); 185 186 /* KVM */ 187 void icp_get_kvm_state(ICPState *icp); 188 int icp_set_kvm_state(ICPState *icp, Error **errp); 189 void icp_synchronize_state(ICPState *icp); 190 void icp_kvm_realize(DeviceState *dev, Error **errp); 191 192 void ics_get_kvm_state(ICSState *ics); 193 int ics_set_kvm_state_one(ICSState *ics, int srcno, Error **errp); 194 int ics_set_kvm_state(ICSState *ics, Error **errp); 195 void ics_synchronize_state(ICSState *ics); 196 void ics_kvm_set_irq(ICSState *ics, int srcno, int val); 197 198 #endif /* XICS_H */ 199