1 /* 2 * Microchip PolarFire SoC machine interface 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2 or later, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef HW_MICROCHIP_PFSOC_H 23 #define HW_MICROCHIP_PFSOC_H 24 25 #include "hw/boards.h" 26 #include "hw/char/mchp_pfsoc_mmuart.h" 27 #include "hw/cpu/cluster.h" 28 #include "hw/dma/sifive_pdma.h" 29 #include "hw/misc/mchp_pfsoc_dmc.h" 30 #include "hw/misc/mchp_pfsoc_ioscb.h" 31 #include "hw/misc/mchp_pfsoc_sysreg.h" 32 #include "hw/net/cadence_gem.h" 33 #include "hw/sd/cadence_sdhci.h" 34 #include "hw/riscv/riscv_hart.h" 35 36 typedef struct MicrochipPFSoCState { 37 /*< private >*/ 38 DeviceState parent_obj; 39 40 /*< public >*/ 41 CPUClusterState e_cluster; 42 CPUClusterState u_cluster; 43 RISCVHartArrayState e_cpus; 44 RISCVHartArrayState u_cpus; 45 DeviceState *plic; 46 MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; 47 MchpPfSoCDdrCfgState ddr_cfg; 48 MchpPfSoCIoscbState ioscb; 49 MchpPfSoCMMUartState *serial0; 50 MchpPfSoCMMUartState *serial1; 51 MchpPfSoCMMUartState *serial2; 52 MchpPfSoCMMUartState *serial3; 53 MchpPfSoCMMUartState *serial4; 54 MchpPfSoCSysregState sysreg; 55 SiFivePDMAState dma; 56 CadenceGEMState gem0; 57 CadenceGEMState gem1; 58 CadenceSDHCIState sdhci; 59 } MicrochipPFSoCState; 60 61 #define TYPE_MICROCHIP_PFSOC "microchip.pfsoc" 62 #define MICROCHIP_PFSOC(obj) \ 63 OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC) 64 65 typedef struct MicrochipIcicleKitState { 66 /*< private >*/ 67 MachineState parent_obj; 68 69 /*< public >*/ 70 MicrochipPFSoCState soc; 71 } MicrochipIcicleKitState; 72 73 #define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \ 74 MACHINE_TYPE_NAME("microchip-icicle-kit") 75 #define MICROCHIP_ICICLE_KIT_MACHINE(obj) \ 76 OBJECT_CHECK(MicrochipIcicleKitState, (obj), \ 77 TYPE_MICROCHIP_ICICLE_KIT_MACHINE) 78 79 enum { 80 MICROCHIP_PFSOC_RSVD0, 81 MICROCHIP_PFSOC_DEBUG, 82 MICROCHIP_PFSOC_E51_DTIM, 83 MICROCHIP_PFSOC_BUSERR_UNIT0, 84 MICROCHIP_PFSOC_BUSERR_UNIT1, 85 MICROCHIP_PFSOC_BUSERR_UNIT2, 86 MICROCHIP_PFSOC_BUSERR_UNIT3, 87 MICROCHIP_PFSOC_BUSERR_UNIT4, 88 MICROCHIP_PFSOC_CLINT, 89 MICROCHIP_PFSOC_L2CC, 90 MICROCHIP_PFSOC_DMA, 91 MICROCHIP_PFSOC_L2LIM, 92 MICROCHIP_PFSOC_PLIC, 93 MICROCHIP_PFSOC_MMUART0, 94 MICROCHIP_PFSOC_WDOG0, 95 MICROCHIP_PFSOC_SYSREG, 96 MICROCHIP_PFSOC_AXISW, 97 MICROCHIP_PFSOC_MPUCFG, 98 MICROCHIP_PFSOC_FMETER, 99 MICROCHIP_PFSOC_DDR_SGMII_PHY, 100 MICROCHIP_PFSOC_EMMC_SD, 101 MICROCHIP_PFSOC_DDR_CFG, 102 MICROCHIP_PFSOC_MMUART1, 103 MICROCHIP_PFSOC_MMUART2, 104 MICROCHIP_PFSOC_MMUART3, 105 MICROCHIP_PFSOC_MMUART4, 106 MICROCHIP_PFSOC_WDOG1, 107 MICROCHIP_PFSOC_WDOG2, 108 MICROCHIP_PFSOC_WDOG3, 109 MICROCHIP_PFSOC_WDOG4, 110 MICROCHIP_PFSOC_SPI0, 111 MICROCHIP_PFSOC_SPI1, 112 MICROCHIP_PFSOC_I2C0, 113 MICROCHIP_PFSOC_I2C1, 114 MICROCHIP_PFSOC_CAN0, 115 MICROCHIP_PFSOC_CAN1, 116 MICROCHIP_PFSOC_GEM0, 117 MICROCHIP_PFSOC_GEM1, 118 MICROCHIP_PFSOC_GPIO0, 119 MICROCHIP_PFSOC_GPIO1, 120 MICROCHIP_PFSOC_GPIO2, 121 MICROCHIP_PFSOC_RTC, 122 MICROCHIP_PFSOC_ENVM_CFG, 123 MICROCHIP_PFSOC_ENVM_DATA, 124 MICROCHIP_PFSOC_USB, 125 MICROCHIP_PFSOC_QSPI_XIP, 126 MICROCHIP_PFSOC_IOSCB, 127 MICROCHIP_PFSOC_FABRIC_FIC0, 128 MICROCHIP_PFSOC_FABRIC_FIC1, 129 MICROCHIP_PFSOC_FABRIC_FIC3, 130 MICROCHIP_PFSOC_DRAM_LO, 131 MICROCHIP_PFSOC_DRAM_LO_ALIAS, 132 MICROCHIP_PFSOC_DRAM_HI, 133 MICROCHIP_PFSOC_DRAM_HI_ALIAS 134 }; 135 136 enum { 137 MICROCHIP_PFSOC_DMA_IRQ0 = 5, 138 MICROCHIP_PFSOC_DMA_IRQ1 = 6, 139 MICROCHIP_PFSOC_DMA_IRQ2 = 7, 140 MICROCHIP_PFSOC_DMA_IRQ3 = 8, 141 MICROCHIP_PFSOC_DMA_IRQ4 = 9, 142 MICROCHIP_PFSOC_DMA_IRQ5 = 10, 143 MICROCHIP_PFSOC_DMA_IRQ6 = 11, 144 MICROCHIP_PFSOC_DMA_IRQ7 = 12, 145 MICROCHIP_PFSOC_GEM0_IRQ = 64, 146 MICROCHIP_PFSOC_GEM1_IRQ = 70, 147 MICROCHIP_PFSOC_EMMC_SD_IRQ = 88, 148 MICROCHIP_PFSOC_MMUART0_IRQ = 90, 149 MICROCHIP_PFSOC_MMUART1_IRQ = 91, 150 MICROCHIP_PFSOC_MMUART2_IRQ = 92, 151 MICROCHIP_PFSOC_MMUART3_IRQ = 93, 152 MICROCHIP_PFSOC_MMUART4_IRQ = 94, 153 MICROCHIP_PFSOC_MAILBOX_IRQ = 96, 154 }; 155 156 #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 157 #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 158 159 #define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187 160 #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 161 #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x00 162 #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 163 #define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000 164 #define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80 165 #define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000 166 #define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000 167 168 #endif /* HW_MICROCHIP_PFSOC_H */ 169