1 /* 2 * QEMU RISC-V Hart Array interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * Holds the state of a heterogenous array of RISC-V harts 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef HW_RISCV_HART_H 22 #define HW_RISCV_HART_H 23 24 #include "hw/sysbus.h" 25 #include "target/riscv/cpu.h" 26 #include "qom/object.h" 27 28 #define TYPE_RISCV_HART_ARRAY "riscv.hart_array" 29 30 typedef struct RISCVHartArrayState RISCVHartArrayState; 31 DECLARE_INSTANCE_CHECKER(RISCVHartArrayState, RISCV_HART_ARRAY, 32 TYPE_RISCV_HART_ARRAY) 33 34 struct RISCVHartArrayState { 35 /*< private >*/ 36 SysBusDevice parent_obj; 37 38 /*< public >*/ 39 uint32_t num_harts; 40 uint32_t hartid_base; 41 char *cpu_type; 42 RISCVCPU *harts; 43 }; 44 45 #endif 46