1*1a6981bbSBernhard Beschow #ifndef HW_SOUTHBRIDGE_ICH9_H 2*1a6981bbSBernhard Beschow #define HW_SOUTHBRIDGE_ICH9_H 3*1a6981bbSBernhard Beschow 4*1a6981bbSBernhard Beschow #include "hw/isa/apm.h" 5*1a6981bbSBernhard Beschow #include "hw/acpi/ich9.h" 6*1a6981bbSBernhard Beschow #include "hw/intc/ioapic.h" 7*1a6981bbSBernhard Beschow #include "hw/pci/pci.h" 8*1a6981bbSBernhard Beschow #include "hw/pci/pci_device.h" 9*1a6981bbSBernhard Beschow #include "exec/memory.h" 10*1a6981bbSBernhard Beschow #include "qemu/notify.h" 11*1a6981bbSBernhard Beschow #include "qom/object.h" 12*1a6981bbSBernhard Beschow 13*1a6981bbSBernhard Beschow void ich9_generate_smi(void); 14*1a6981bbSBernhard Beschow 15*1a6981bbSBernhard Beschow #define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */ 16*1a6981bbSBernhard Beschow 17*1a6981bbSBernhard Beschow #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" 18*1a6981bbSBernhard Beschow OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE) 19*1a6981bbSBernhard Beschow 20*1a6981bbSBernhard Beschow struct ICH9LPCState { 21*1a6981bbSBernhard Beschow /* ICH9 LPC PCI to ISA bridge */ 22*1a6981bbSBernhard Beschow PCIDevice d; 23*1a6981bbSBernhard Beschow 24*1a6981bbSBernhard Beschow /* (pci device, intx) -> pirq 25*1a6981bbSBernhard Beschow * In real chipset case, the unused slots are never used 26*1a6981bbSBernhard Beschow * as ICH9 supports only D25-D31 irq routing. 27*1a6981bbSBernhard Beschow * On the other hand in qemu case, any slot/function can be populated 28*1a6981bbSBernhard Beschow * via command line option. 29*1a6981bbSBernhard Beschow * So fallback interrupt routing for any devices in any slots is necessary. 30*1a6981bbSBernhard Beschow */ 31*1a6981bbSBernhard Beschow uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; 32*1a6981bbSBernhard Beschow 33*1a6981bbSBernhard Beschow APMState apm; 34*1a6981bbSBernhard Beschow ICH9LPCPMRegs pm; 35*1a6981bbSBernhard Beschow uint32_t sci_level; /* track sci level */ 36*1a6981bbSBernhard Beschow uint8_t sci_gsi; 37*1a6981bbSBernhard Beschow 38*1a6981bbSBernhard Beschow /* 2.24 Pin Straps */ 39*1a6981bbSBernhard Beschow struct { 40*1a6981bbSBernhard Beschow bool spkr_hi; 41*1a6981bbSBernhard Beschow } pin_strap; 42*1a6981bbSBernhard Beschow 43*1a6981bbSBernhard Beschow /* 10.1 Chipset Configuration registers(Memory Space) 44*1a6981bbSBernhard Beschow which is pointed by RCBA */ 45*1a6981bbSBernhard Beschow uint8_t chip_config[ICH9_CC_SIZE]; 46*1a6981bbSBernhard Beschow 47*1a6981bbSBernhard Beschow /* 48*1a6981bbSBernhard Beschow * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0) 49*1a6981bbSBernhard Beschow * 50*1a6981bbSBernhard Beschow * register contents and IO memory region 51*1a6981bbSBernhard Beschow */ 52*1a6981bbSBernhard Beschow uint8_t rst_cnt; 53*1a6981bbSBernhard Beschow MemoryRegion rst_cnt_mem; 54*1a6981bbSBernhard Beschow 55*1a6981bbSBernhard Beschow /* SMI feature negotiation via fw_cfg */ 56*1a6981bbSBernhard Beschow uint64_t smi_host_features; /* guest-invisible, host endian */ 57*1a6981bbSBernhard Beschow uint8_t smi_host_features_le[8]; /* guest-visible, read-only, little 58*1a6981bbSBernhard Beschow * endian uint64_t */ 59*1a6981bbSBernhard Beschow uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little 60*1a6981bbSBernhard Beschow * endian uint64_t */ 61*1a6981bbSBernhard Beschow uint8_t smi_features_ok; /* guest-visible, read-only; selecting it 62*1a6981bbSBernhard Beschow * triggers feature lockdown */ 63*1a6981bbSBernhard Beschow uint64_t smi_negotiated_features; /* guest-invisible, host endian */ 64*1a6981bbSBernhard Beschow 65*1a6981bbSBernhard Beschow MemoryRegion rcrb_mem; /* root complex register block */ 66*1a6981bbSBernhard Beschow Notifier machine_ready; 67*1a6981bbSBernhard Beschow 68*1a6981bbSBernhard Beschow qemu_irq gsi[IOAPIC_NUM_PINS]; 69*1a6981bbSBernhard Beschow }; 70*1a6981bbSBernhard Beschow 71*1a6981bbSBernhard Beschow #define ICH9_MASK(bit, ms_bit, ls_bit) \ 72*1a6981bbSBernhard Beschow ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) 73*1a6981bbSBernhard Beschow 74*1a6981bbSBernhard Beschow /* ICH9: Chipset Configuration Registers */ 75*1a6981bbSBernhard Beschow #define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) 76*1a6981bbSBernhard Beschow 77*1a6981bbSBernhard Beschow #define ICH9_CC 78*1a6981bbSBernhard Beschow #define ICH9_CC_D28IP 0x310C 79*1a6981bbSBernhard Beschow #define ICH9_CC_D28IP_SHIFT 4 80*1a6981bbSBernhard Beschow #define ICH9_CC_D28IP_MASK 0xf 81*1a6981bbSBernhard Beschow #define ICH9_CC_D28IP_DEFAULT 0x00214321 82*1a6981bbSBernhard Beschow #define ICH9_CC_D31IR 0x3140 83*1a6981bbSBernhard Beschow #define ICH9_CC_D30IR 0x3142 84*1a6981bbSBernhard Beschow #define ICH9_CC_D29IR 0x3144 85*1a6981bbSBernhard Beschow #define ICH9_CC_D28IR 0x3146 86*1a6981bbSBernhard Beschow #define ICH9_CC_D27IR 0x3148 87*1a6981bbSBernhard Beschow #define ICH9_CC_D26IR 0x314C 88*1a6981bbSBernhard Beschow #define ICH9_CC_D25IR 0x3150 89*1a6981bbSBernhard Beschow #define ICH9_CC_DIR_DEFAULT 0x3210 90*1a6981bbSBernhard Beschow #define ICH9_CC_D30IR_DEFAULT 0x0 91*1a6981bbSBernhard Beschow #define ICH9_CC_DIR_SHIFT 4 92*1a6981bbSBernhard Beschow #define ICH9_CC_DIR_MASK 0x7 93*1a6981bbSBernhard Beschow #define ICH9_CC_OIC 0x31FF 94*1a6981bbSBernhard Beschow #define ICH9_CC_OIC_AEN 0x1 95*1a6981bbSBernhard Beschow #define ICH9_CC_GCS 0x3410 96*1a6981bbSBernhard Beschow #define ICH9_CC_GCS_DEFAULT 0x00000020 97*1a6981bbSBernhard Beschow #define ICH9_CC_GCS_NO_REBOOT (1 << 5) 98*1a6981bbSBernhard Beschow 99*1a6981bbSBernhard Beschow /* D28:F[0-5] */ 100*1a6981bbSBernhard Beschow #define ICH9_PCIE_DEV 28 101*1a6981bbSBernhard Beschow #define ICH9_PCIE_FUNC_MAX 6 102*1a6981bbSBernhard Beschow 103*1a6981bbSBernhard Beschow 104*1a6981bbSBernhard Beschow /* D29:F0 USB UHCI Controller #1 */ 105*1a6981bbSBernhard Beschow #define ICH9_USB_UHCI1_DEV 29 106*1a6981bbSBernhard Beschow #define ICH9_USB_UHCI1_FUNC 0 107*1a6981bbSBernhard Beschow 108*1a6981bbSBernhard Beschow /* D30:F0 DMI-to-PCI bridge */ 109*1a6981bbSBernhard Beschow #define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE" 110*1a6981bbSBernhard Beschow #define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0 111*1a6981bbSBernhard Beschow 112*1a6981bbSBernhard Beschow #define ICH9_D2P_BRIDGE_DEV 30 113*1a6981bbSBernhard Beschow #define ICH9_D2P_BRIDGE_FUNC 0 114*1a6981bbSBernhard Beschow 115*1a6981bbSBernhard Beschow #define ICH9_D2P_SECONDARY_DEFAULT (256 - 8) 116*1a6981bbSBernhard Beschow 117*1a6981bbSBernhard Beschow #define ICH9_D2P_A2_REVISION 0x92 118*1a6981bbSBernhard Beschow 119*1a6981bbSBernhard Beschow /* D31:F0 LPC Processor Interface */ 120*1a6981bbSBernhard Beschow #define ICH9_RST_CNT_IOPORT 0xCF9 121*1a6981bbSBernhard Beschow 122*1a6981bbSBernhard Beschow /* D31:F1 LPC controller */ 123*1a6981bbSBernhard Beschow #define ICH9_A2_LPC "ICH9 A2 LPC" 124*1a6981bbSBernhard Beschow #define ICH9_A2_LPC_SAVEVM_VERSION 0 125*1a6981bbSBernhard Beschow 126*1a6981bbSBernhard Beschow #define ICH9_LPC_DEV 31 127*1a6981bbSBernhard Beschow #define ICH9_LPC_FUNC 0 128*1a6981bbSBernhard Beschow 129*1a6981bbSBernhard Beschow #define ICH9_A2_LPC_REVISION 0x2 130*1a6981bbSBernhard Beschow #define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ 131*1a6981bbSBernhard Beschow 132*1a6981bbSBernhard Beschow #define ICH9_LPC_PMBASE 0x40 133*1a6981bbSBernhard Beschow #define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ICH9_MASK(32, 15, 7) 134*1a6981bbSBernhard Beschow #define ICH9_LPC_PMBASE_RTE 0x1 135*1a6981bbSBernhard Beschow #define ICH9_LPC_PMBASE_DEFAULT 0x1 136*1a6981bbSBernhard Beschow 137*1a6981bbSBernhard Beschow #define ICH9_LPC_ACPI_CTRL 0x44 138*1a6981bbSBernhard Beschow #define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 139*1a6981bbSBernhard Beschow #define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ICH9_MASK(8, 2, 0) 140*1a6981bbSBernhard Beschow #define ICH9_LPC_ACPI_CTRL_9 0x0 141*1a6981bbSBernhard Beschow #define ICH9_LPC_ACPI_CTRL_10 0x1 142*1a6981bbSBernhard Beschow #define ICH9_LPC_ACPI_CTRL_11 0x2 143*1a6981bbSBernhard Beschow #define ICH9_LPC_ACPI_CTRL_20 0x4 144*1a6981bbSBernhard Beschow #define ICH9_LPC_ACPI_CTRL_21 0x5 145*1a6981bbSBernhard Beschow #define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0 146*1a6981bbSBernhard Beschow 147*1a6981bbSBernhard Beschow #define ICH9_LPC_PIRQA_ROUT 0x60 148*1a6981bbSBernhard Beschow #define ICH9_LPC_PIRQB_ROUT 0x61 149*1a6981bbSBernhard Beschow #define ICH9_LPC_PIRQC_ROUT 0x62 150*1a6981bbSBernhard Beschow #define ICH9_LPC_PIRQD_ROUT 0x63 151*1a6981bbSBernhard Beschow 152*1a6981bbSBernhard Beschow #define ICH9_LPC_PIRQE_ROUT 0x68 153*1a6981bbSBernhard Beschow #define ICH9_LPC_PIRQF_ROUT 0x69 154*1a6981bbSBernhard Beschow #define ICH9_LPC_PIRQG_ROUT 0x6a 155*1a6981bbSBernhard Beschow #define ICH9_LPC_PIRQH_ROUT 0x6b 156*1a6981bbSBernhard Beschow 157*1a6981bbSBernhard Beschow #define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 158*1a6981bbSBernhard Beschow #define ICH9_LPC_PIRQ_ROUT_MASK ICH9_MASK(8, 3, 0) 159*1a6981bbSBernhard Beschow #define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 160*1a6981bbSBernhard Beschow 161*1a6981bbSBernhard Beschow #define ICH9_LPC_GEN_PMCON_1 0xa0 162*1a6981bbSBernhard Beschow #define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4) 163*1a6981bbSBernhard Beschow #define ICH9_LPC_GEN_PMCON_2 0xa2 164*1a6981bbSBernhard Beschow #define ICH9_LPC_GEN_PMCON_3 0xa4 165*1a6981bbSBernhard Beschow #define ICH9_LPC_GEN_PMCON_LOCK 0xa6 166*1a6981bbSBernhard Beschow 167*1a6981bbSBernhard Beschow #define ICH9_LPC_RCBA 0xf0 168*1a6981bbSBernhard Beschow #define ICH9_LPC_RCBA_BA_MASK ICH9_MASK(32, 31, 14) 169*1a6981bbSBernhard Beschow #define ICH9_LPC_RCBA_EN 0x1 170*1a6981bbSBernhard Beschow #define ICH9_LPC_RCBA_DEFAULT 0x0 171*1a6981bbSBernhard Beschow 172*1a6981bbSBernhard Beschow #define ICH9_LPC_PIC_NUM_PINS 16 173*1a6981bbSBernhard Beschow #define ICH9_LPC_IOAPIC_NUM_PINS 24 174*1a6981bbSBernhard Beschow 175*1a6981bbSBernhard Beschow #define ICH9_GPIO_GSI "gsi" 176*1a6981bbSBernhard Beschow 177*1a6981bbSBernhard Beschow /* D31:F2 SATA Controller #1 */ 178*1a6981bbSBernhard Beschow #define ICH9_SATA1_DEV 31 179*1a6981bbSBernhard Beschow #define ICH9_SATA1_FUNC 2 180*1a6981bbSBernhard Beschow 181*1a6981bbSBernhard Beschow /* D31:F0 power management I/O registers 182*1a6981bbSBernhard Beschow offset from the address ICH9_LPC_PMBASE */ 183*1a6981bbSBernhard Beschow 184*1a6981bbSBernhard Beschow /* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ 185*1a6981bbSBernhard Beschow #define ICH9_PMIO_SIZE 128 186*1a6981bbSBernhard Beschow #define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) 187*1a6981bbSBernhard Beschow 188*1a6981bbSBernhard Beschow #define ICH9_PMIO_PM1_STS 0x00 189*1a6981bbSBernhard Beschow #define ICH9_PMIO_PM1_EN 0x02 190*1a6981bbSBernhard Beschow #define ICH9_PMIO_PM1_CNT 0x04 191*1a6981bbSBernhard Beschow #define ICH9_PMIO_PM1_TMR 0x08 192*1a6981bbSBernhard Beschow #define ICH9_PMIO_GPE0_STS 0x20 193*1a6981bbSBernhard Beschow #define ICH9_PMIO_GPE0_EN 0x28 194*1a6981bbSBernhard Beschow #define ICH9_PMIO_GPE0_LEN 16 195*1a6981bbSBernhard Beschow #define ICH9_PMIO_SMI_EN 0x30 196*1a6981bbSBernhard Beschow #define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) 197*1a6981bbSBernhard Beschow #define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13) 198*1a6981bbSBernhard Beschow #define ICH9_PMIO_SMI_STS 0x34 199*1a6981bbSBernhard Beschow #define ICH9_PMIO_TCO_RLD 0x60 200*1a6981bbSBernhard Beschow #define ICH9_PMIO_TCO_LEN 32 201*1a6981bbSBernhard Beschow 202*1a6981bbSBernhard Beschow /* FADT ACPI_ENABLE/ACPI_DISABLE */ 203*1a6981bbSBernhard Beschow #define ICH9_APM_ACPI_ENABLE 0x2 204*1a6981bbSBernhard Beschow #define ICH9_APM_ACPI_DISABLE 0x3 205*1a6981bbSBernhard Beschow 206*1a6981bbSBernhard Beschow 207*1a6981bbSBernhard Beschow /* D31:F3 SMBus controller */ 208*1a6981bbSBernhard Beschow #define TYPE_ICH9_SMB_DEVICE "ICH9-SMB" 209*1a6981bbSBernhard Beschow 210*1a6981bbSBernhard Beschow #define ICH9_A2_SMB_REVISION 0x02 211*1a6981bbSBernhard Beschow #define ICH9_SMB_PI 0x00 212*1a6981bbSBernhard Beschow 213*1a6981bbSBernhard Beschow #define ICH9_SMB_SMBMBAR0 0x10 214*1a6981bbSBernhard Beschow #define ICH9_SMB_SMBMBAR1 0x14 215*1a6981bbSBernhard Beschow #define ICH9_SMB_SMBM_BAR 0 216*1a6981bbSBernhard Beschow #define ICH9_SMB_SMBM_SIZE (1 << 8) 217*1a6981bbSBernhard Beschow #define ICH9_SMB_SMB_BASE 0x20 218*1a6981bbSBernhard Beschow #define ICH9_SMB_SMB_BASE_BAR 4 219*1a6981bbSBernhard Beschow #define ICH9_SMB_SMB_BASE_SIZE (1 << 5) 220*1a6981bbSBernhard Beschow #define ICH9_SMB_HOSTC 0x40 221*1a6981bbSBernhard Beschow #define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) 222*1a6981bbSBernhard Beschow #define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) 223*1a6981bbSBernhard Beschow #define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) 224*1a6981bbSBernhard Beschow #define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) 225*1a6981bbSBernhard Beschow 226*1a6981bbSBernhard Beschow /* D31:F3 SMBus I/O and memory mapped I/O registers */ 227*1a6981bbSBernhard Beschow #define ICH9_SMB_DEV 31 228*1a6981bbSBernhard Beschow #define ICH9_SMB_FUNC 3 229*1a6981bbSBernhard Beschow 230*1a6981bbSBernhard Beschow #define ICH9_SMB_HST_STS 0x00 231*1a6981bbSBernhard Beschow #define ICH9_SMB_HST_CNT 0x02 232*1a6981bbSBernhard Beschow #define ICH9_SMB_HST_CMD 0x03 233*1a6981bbSBernhard Beschow #define ICH9_SMB_XMIT_SLVA 0x04 234*1a6981bbSBernhard Beschow #define ICH9_SMB_HST_D0 0x05 235*1a6981bbSBernhard Beschow #define ICH9_SMB_HST_D1 0x06 236*1a6981bbSBernhard Beschow #define ICH9_SMB_HOST_BLOCK_DB 0x07 237*1a6981bbSBernhard Beschow 238*1a6981bbSBernhard Beschow #define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" 239*1a6981bbSBernhard Beschow 240*1a6981bbSBernhard Beschow /* bit positions used in fw_cfg SMI feature negotiation */ 241*1a6981bbSBernhard Beschow #define ICH9_LPC_SMI_F_BROADCAST_BIT 0 242*1a6981bbSBernhard Beschow #define ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT 1 243*1a6981bbSBernhard Beschow #define ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT 2 244*1a6981bbSBernhard Beschow 245*1a6981bbSBernhard Beschow #endif /* HW_SOUTHBRIDGE_ICH9_H */ 246