1fff123b8SPhilippe Mathieu-Daudé /* 2fff123b8SPhilippe Mathieu-Daudé * QEMU PIIX South Bridge Emulation 3fff123b8SPhilippe Mathieu-Daudé * 4fff123b8SPhilippe Mathieu-Daudé * Copyright (c) 2006 Fabrice Bellard 5e29f2379SPhilippe Mathieu-Daudé * Copyright (c) 2018 Hervé Poussineau 6fff123b8SPhilippe Mathieu-Daudé * 7fff123b8SPhilippe Mathieu-Daudé * This work is licensed under the terms of the GNU GPL, version 2 or later. 8fff123b8SPhilippe Mathieu-Daudé * See the COPYING file in the top-level directory. 9fff123b8SPhilippe Mathieu-Daudé * 10fff123b8SPhilippe Mathieu-Daudé */ 11fff123b8SPhilippe Mathieu-Daudé 12fff123b8SPhilippe Mathieu-Daudé #ifndef HW_SOUTHBRIDGE_PIIX_H 13fff123b8SPhilippe Mathieu-Daudé #define HW_SOUTHBRIDGE_PIIX_H 14fff123b8SPhilippe Mathieu-Daudé 15edf5ca5dSMarkus Armbruster #include "hw/pci/pci_device.h" 16fff123b8SPhilippe Mathieu-Daudé 174b19de14SPhilippe Mathieu-Daudé /* PIRQRC[A:D]: PIRQx Route Control Registers */ 184b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCA 0x60 194b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCB 0x61 204b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCC 0x62 214b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCD 0x63 224b19de14SPhilippe Mathieu-Daudé 230063454aSPhilippe Mathieu-Daudé /* 240063454aSPhilippe Mathieu-Daudé * Reset Control Register: PCI-accessible ISA-Compatible Register at address 250063454aSPhilippe Mathieu-Daudé * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). 260063454aSPhilippe Mathieu-Daudé */ 270063454aSPhilippe Mathieu-Daudé #define PIIX_RCR_IOPORT 0xcf9 280063454aSPhilippe Mathieu-Daudé 2914a026ddSPhilippe Mathieu-Daudé #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ 3014a026ddSPhilippe Mathieu-Daudé #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ 3114a026ddSPhilippe Mathieu-Daudé 32db1015e9SEduardo Habkost struct PIIXState { 3314a026ddSPhilippe Mathieu-Daudé PCIDevice dev; 3414a026ddSPhilippe Mathieu-Daudé 3514a026ddSPhilippe Mathieu-Daudé /* 3614a026ddSPhilippe Mathieu-Daudé * bitmap to track pic levels. 3714a026ddSPhilippe Mathieu-Daudé * The pic level is the logical OR of all the PCI irqs mapped to it 3814a026ddSPhilippe Mathieu-Daudé * So one PIC level is tracked by PIIX_NUM_PIRQS bits. 3914a026ddSPhilippe Mathieu-Daudé * 4014a026ddSPhilippe Mathieu-Daudé * PIRQ is mapped to PIC pins, we track it by 4114a026ddSPhilippe Mathieu-Daudé * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with 4214a026ddSPhilippe Mathieu-Daudé * pic_irq * PIIX_NUM_PIRQS + pirq 4314a026ddSPhilippe Mathieu-Daudé */ 4414a026ddSPhilippe Mathieu-Daudé #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 4514a026ddSPhilippe Mathieu-Daudé #error "unable to encode pic state in 64bit in pic_levels." 4614a026ddSPhilippe Mathieu-Daudé #endif 4714a026ddSPhilippe Mathieu-Daudé uint64_t pic_levels; 4814a026ddSPhilippe Mathieu-Daudé 4914a026ddSPhilippe Mathieu-Daudé qemu_irq *pic; 5014a026ddSPhilippe Mathieu-Daudé 5114a026ddSPhilippe Mathieu-Daudé /* This member isn't used. Just for save/load compatibility */ 5214a026ddSPhilippe Mathieu-Daudé int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; 5314a026ddSPhilippe Mathieu-Daudé 5414a026ddSPhilippe Mathieu-Daudé /* Reset Control Register contents */ 5514a026ddSPhilippe Mathieu-Daudé uint8_t rcr; 5614a026ddSPhilippe Mathieu-Daudé 5714a026ddSPhilippe Mathieu-Daudé /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ 5814a026ddSPhilippe Mathieu-Daudé MemoryRegion rcr_mem; 59db1015e9SEduardo Habkost }; 60db1015e9SEduardo Habkost typedef struct PIIXState PIIX3State; 6114a026ddSPhilippe Mathieu-Daudé 62fe47ad3aSEduardo Habkost #define TYPE_PIIX3_PCI_DEVICE "pci-piix3" 638110fa1dSEduardo Habkost DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, 648110fa1dSEduardo Habkost TYPE_PIIX3_PCI_DEVICE) 65fe47ad3aSEduardo Habkost 663963e139SBernhard Beschow #define TYPE_PIIX3_DEVICE "PIIX3" 673963e139SBernhard Beschow #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" 683963e139SBernhard Beschow #define TYPE_PIIX4_PCI_DEVICE "piix4-isa" 693963e139SBernhard Beschow 70fff123b8SPhilippe Mathieu-Daudé #endif 71