1 2 /* 3 * QEMU model of the Ibex SPI Controller 4 * SPEC Reference: https://docs.opentitan.org/hw/ip/spi_host/doc/ 5 * 6 * Copyright (C) 2022 Western Digital 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #ifndef IBEX_SPI_HOST_H 28 #define IBEX_SPI_HOST_H 29 30 #include "hw/sysbus.h" 31 #include "hw/hw.h" 32 #include "hw/ssi/ssi.h" 33 #include "qemu/fifo8.h" 34 #include "qom/object.h" 35 #include "hw/registerfields.h" 36 #include "qemu/timer.h" 37 38 #define TYPE_IBEX_SPI_HOST "ibex-spi" 39 #define IBEX_SPI_HOST(obj) \ 40 OBJECT_CHECK(IbexSPIHostState, (obj), TYPE_IBEX_SPI_HOST) 41 42 /* SPI Registers */ 43 #define IBEX_SPI_HOST_INTR_STATE (0x00 / 4) /* rw1c */ 44 #define IBEX_SPI_HOST_INTR_ENABLE (0x04 / 4) /* rw */ 45 #define IBEX_SPI_HOST_INTR_TEST (0x08 / 4) /* wo */ 46 #define IBEX_SPI_HOST_ALERT_TEST (0x0c / 4) /* wo */ 47 #define IBEX_SPI_HOST_CONTROL (0x10 / 4) /* rw */ 48 #define IBEX_SPI_HOST_STATUS (0x14 / 4) /* ro */ 49 #define IBEX_SPI_HOST_CONFIGOPTS (0x18 / 4) /* rw */ 50 #define IBEX_SPI_HOST_CSID (0x1c / 4) /* rw */ 51 #define IBEX_SPI_HOST_COMMAND (0x20 / 4) /* wo */ 52 /* RX/TX Modelled by FIFO */ 53 #define IBEX_SPI_HOST_RXDATA (0x24 / 4) 54 #define IBEX_SPI_HOST_TXDATA (0x28 / 4) 55 56 #define IBEX_SPI_HOST_ERROR_ENABLE (0x2c / 4) /* rw */ 57 #define IBEX_SPI_HOST_ERROR_STATUS (0x30 / 4) /* rw1c */ 58 #define IBEX_SPI_HOST_EVENT_ENABLE (0x34 / 4) /* rw */ 59 60 /* FIFO Len in Bytes */ 61 #define IBEX_SPI_HOST_TXFIFO_LEN 288 62 #define IBEX_SPI_HOST_RXFIFO_LEN 256 63 64 /* Max Register (Based on addr) */ 65 #define IBEX_SPI_HOST_MAX_REGS (IBEX_SPI_HOST_EVENT_ENABLE + 1) 66 67 /* MISC */ 68 #define TX_INTERRUPT_TRIGGER_DELAY_NS 100 69 #define BIDIRECTIONAL_TRANSFER 3 70 71 typedef struct { 72 /* <private> */ 73 SysBusDevice parent_obj; 74 75 /* <public> */ 76 MemoryRegion mmio; 77 uint32_t regs[IBEX_SPI_HOST_MAX_REGS]; 78 /* Multi-reg that sets config opts per CS */ 79 uint32_t *config_opts; 80 Fifo8 rx_fifo; 81 Fifo8 tx_fifo; 82 QEMUTimer *fifo_trigger_handle; 83 84 qemu_irq event; 85 qemu_irq host_err; 86 uint32_t num_cs; 87 qemu_irq *cs_lines; 88 SSIBus *ssi; 89 90 /* Used to track the init status, for replicating TXDATA ghost writes */ 91 bool init_status; 92 } IbexSPIHostState; 93 94 #endif 95