169fbfb8fSHao Wu /* 269fbfb8fSHao Wu * Nuvoton Peripheral SPI Module 369fbfb8fSHao Wu * 469fbfb8fSHao Wu * Copyright 2023 Google LLC 569fbfb8fSHao Wu * 669fbfb8fSHao Wu * This program is free software; you can redistribute it and/or modify it 769fbfb8fSHao Wu * under the terms of the GNU General Public License as published by the 869fbfb8fSHao Wu * Free Software Foundation; either version 2 of the License, or 969fbfb8fSHao Wu * (at your option) any later version. 1069fbfb8fSHao Wu * 1169fbfb8fSHao Wu * This program is distributed in the hope that it will be useful, but WITHOUT 1269fbfb8fSHao Wu * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1369fbfb8fSHao Wu * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 1469fbfb8fSHao Wu * for more details. 1569fbfb8fSHao Wu */ 1669fbfb8fSHao Wu #ifndef NPCM_PSPI_H 1769fbfb8fSHao Wu #define NPCM_PSPI_H 1869fbfb8fSHao Wu 1969fbfb8fSHao Wu #include "hw/ssi/ssi.h" 2069fbfb8fSHao Wu #include "hw/sysbus.h" 2169fbfb8fSHao Wu 2269fbfb8fSHao Wu /* 2369fbfb8fSHao Wu * Number of registers in our device state structure. Don't change this without 2469fbfb8fSHao Wu * incrementing the version_id in the vmstate. 2569fbfb8fSHao Wu */ 2669fbfb8fSHao Wu #define NPCM_PSPI_NR_REGS 3 2769fbfb8fSHao Wu 2869fbfb8fSHao Wu /** 2969fbfb8fSHao Wu * NPCMPSPIState - Device state for one Flash Interface Unit. 3069fbfb8fSHao Wu * @parent: System bus device. 3169fbfb8fSHao Wu * @mmio: Memory region for register access. 3269fbfb8fSHao Wu * @spi: The SPI bus mastered by this controller. 3369fbfb8fSHao Wu * @regs: Register contents. 3469fbfb8fSHao Wu * @irq: The interrupt request queue for this module. 3569fbfb8fSHao Wu * 3669fbfb8fSHao Wu * Each PSPI has a shared bank of registers, and controls up to four chip 3769fbfb8fSHao Wu * selects. Each chip select has a dedicated memory region which may be used to 3869fbfb8fSHao Wu * read and write the flash connected to that chip select as if it were memory. 3969fbfb8fSHao Wu */ 4069fbfb8fSHao Wu typedef struct NPCMPSPIState { 4169fbfb8fSHao Wu SysBusDevice parent; 4269fbfb8fSHao Wu 4369fbfb8fSHao Wu MemoryRegion mmio; 4469fbfb8fSHao Wu 4569fbfb8fSHao Wu SSIBus *spi; 4669fbfb8fSHao Wu uint16_t regs[NPCM_PSPI_NR_REGS]; 4769fbfb8fSHao Wu qemu_irq irq; 4869fbfb8fSHao Wu } NPCMPSPIState; 4969fbfb8fSHao Wu 5069fbfb8fSHao Wu #define TYPE_NPCM_PSPI "npcm-pspi" 5169fbfb8fSHao Wu OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI) 5269fbfb8fSHao Wu 5369fbfb8fSHao Wu #endif /* NPCM_PSPI_H */ 54