1cbb45ff0SFrancisco Iglesias /* 2cbb45ff0SFrancisco Iglesias * Header file for the Xilinx Versal's OSPI controller 3cbb45ff0SFrancisco Iglesias * 4cbb45ff0SFrancisco Iglesias * Copyright (C) 2021 Xilinx Inc 5cbb45ff0SFrancisco Iglesias * Written by Francisco Iglesias <francisco.iglesias@xilinx.com> 6cbb45ff0SFrancisco Iglesias * 7cbb45ff0SFrancisco Iglesias * Permission is hereby granted, free of charge, to any person obtaining a copy 8cbb45ff0SFrancisco Iglesias * of this software and associated documentation files (the "Software"), to deal 9cbb45ff0SFrancisco Iglesias * in the Software without restriction, including without limitation the rights 10cbb45ff0SFrancisco Iglesias * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11cbb45ff0SFrancisco Iglesias * copies of the Software, and to permit persons to whom the Software is 12cbb45ff0SFrancisco Iglesias * furnished to do so, subject to the following conditions: 13cbb45ff0SFrancisco Iglesias * 14cbb45ff0SFrancisco Iglesias * The above copyright notice and this permission notice shall be included in 15cbb45ff0SFrancisco Iglesias * all copies or substantial portions of the Software. 16cbb45ff0SFrancisco Iglesias * 17cbb45ff0SFrancisco Iglesias * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18cbb45ff0SFrancisco Iglesias * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19cbb45ff0SFrancisco Iglesias * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20cbb45ff0SFrancisco Iglesias * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21cbb45ff0SFrancisco Iglesias * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22cbb45ff0SFrancisco Iglesias * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23cbb45ff0SFrancisco Iglesias * THE SOFTWARE. 24cbb45ff0SFrancisco Iglesias */ 25cbb45ff0SFrancisco Iglesias 26cbb45ff0SFrancisco Iglesias /* 27cbb45ff0SFrancisco Iglesias * This is a model of Xilinx Versal's Octal SPI flash memory controller 28cbb45ff0SFrancisco Iglesias * documented in Versal's Technical Reference manual [1] and the Versal ACAP 29cbb45ff0SFrancisco Iglesias * Register reference [2]. 30cbb45ff0SFrancisco Iglesias * 31cbb45ff0SFrancisco Iglesias * References: 32cbb45ff0SFrancisco Iglesias * 33cbb45ff0SFrancisco Iglesias * [1] Versal ACAP Technical Reference Manual, 34cbb45ff0SFrancisco Iglesias * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf 35cbb45ff0SFrancisco Iglesias * 36cbb45ff0SFrancisco Iglesias * [2] Versal ACAP Register Reference, 37*a9bc470eSFrederic Konrad * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/OSPI-Module 38cbb45ff0SFrancisco Iglesias * 39cbb45ff0SFrancisco Iglesias * 40cbb45ff0SFrancisco Iglesias * QEMU interface: 41cbb45ff0SFrancisco Iglesias * + sysbus MMIO region 0: MemoryRegion for the device's registers 42cbb45ff0SFrancisco Iglesias * + sysbus MMIO region 1: MemoryRegion for flash memory linear address space 43cbb45ff0SFrancisco Iglesias * (data transfer). 44cbb45ff0SFrancisco Iglesias * + sysbus IRQ 0: Device interrupt. 45cbb45ff0SFrancisco Iglesias * + Named GPIO input "ospi-mux-sel": 0: enables indirect access mode 46cbb45ff0SFrancisco Iglesias * and 1: enables direct access mode. 47cbb45ff0SFrancisco Iglesias * + Property "dac-with-indac": Allow both direct accesses and indirect 48cbb45ff0SFrancisco Iglesias * accesses simultaneously. 49cbb45ff0SFrancisco Iglesias * + Property "indac-write-disabled": Disable indirect access writes. 50cbb45ff0SFrancisco Iglesias */ 51cbb45ff0SFrancisco Iglesias 5252581c71SMarkus Armbruster #ifndef XLNX_VERSAL_OSPI_H 5352581c71SMarkus Armbruster #define XLNX_VERSAL_OSPI_H 54cbb45ff0SFrancisco Iglesias 55cbb45ff0SFrancisco Iglesias #include "hw/register.h" 56cbb45ff0SFrancisco Iglesias #include "hw/ssi/ssi.h" 57cbb45ff0SFrancisco Iglesias #include "qemu/fifo8.h" 58cbb45ff0SFrancisco Iglesias #include "hw/dma/xlnx_csu_dma.h" 59cbb45ff0SFrancisco Iglesias 60cbb45ff0SFrancisco Iglesias #define TYPE_XILINX_VERSAL_OSPI "xlnx.versal-ospi" 61cbb45ff0SFrancisco Iglesias 62cbb45ff0SFrancisco Iglesias OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalOspi, XILINX_VERSAL_OSPI) 63cbb45ff0SFrancisco Iglesias 64cbb45ff0SFrancisco Iglesias #define XILINX_VERSAL_OSPI_R_MAX (0xfc / 4 + 1) 65cbb45ff0SFrancisco Iglesias 66cbb45ff0SFrancisco Iglesias /* 67cbb45ff0SFrancisco Iglesias * Indirect operations 68cbb45ff0SFrancisco Iglesias */ 69cbb45ff0SFrancisco Iglesias typedef struct IndOp { 70cbb45ff0SFrancisco Iglesias uint32_t flash_addr; 71cbb45ff0SFrancisco Iglesias uint32_t num_bytes; 72cbb45ff0SFrancisco Iglesias uint32_t done_bytes; 73cbb45ff0SFrancisco Iglesias bool completed; 74cbb45ff0SFrancisco Iglesias } IndOp; 75cbb45ff0SFrancisco Iglesias 76cbb45ff0SFrancisco Iglesias struct XlnxVersalOspi { 77cbb45ff0SFrancisco Iglesias SysBusDevice parent_obj; 78cbb45ff0SFrancisco Iglesias 79cbb45ff0SFrancisco Iglesias MemoryRegion iomem; 80cbb45ff0SFrancisco Iglesias MemoryRegion iomem_dac; 81cbb45ff0SFrancisco Iglesias 82cbb45ff0SFrancisco Iglesias uint8_t num_cs; 83cbb45ff0SFrancisco Iglesias qemu_irq *cs_lines; 84cbb45ff0SFrancisco Iglesias 85cbb45ff0SFrancisco Iglesias SSIBus *spi; 86cbb45ff0SFrancisco Iglesias 87cbb45ff0SFrancisco Iglesias Fifo8 rx_fifo; 88cbb45ff0SFrancisco Iglesias Fifo8 tx_fifo; 89cbb45ff0SFrancisco Iglesias 90cbb45ff0SFrancisco Iglesias Fifo8 rx_sram; 91cbb45ff0SFrancisco Iglesias Fifo8 tx_sram; 92cbb45ff0SFrancisco Iglesias 93cbb45ff0SFrancisco Iglesias qemu_irq irq; 94cbb45ff0SFrancisco Iglesias 95cbb45ff0SFrancisco Iglesias XlnxCSUDMA *dma_src; 96cbb45ff0SFrancisco Iglesias bool ind_write_disabled; 97cbb45ff0SFrancisco Iglesias bool dac_with_indac; 98cbb45ff0SFrancisco Iglesias bool dac_enable; 99cbb45ff0SFrancisco Iglesias bool src_dma_inprog; 100cbb45ff0SFrancisco Iglesias 101cbb45ff0SFrancisco Iglesias IndOp rd_ind_op[2]; 102cbb45ff0SFrancisco Iglesias IndOp wr_ind_op[2]; 103cbb45ff0SFrancisco Iglesias 104cbb45ff0SFrancisco Iglesias uint32_t regs[XILINX_VERSAL_OSPI_R_MAX]; 105cbb45ff0SFrancisco Iglesias RegisterInfo regs_info[XILINX_VERSAL_OSPI_R_MAX]; 106cbb45ff0SFrancisco Iglesias 107cbb45ff0SFrancisco Iglesias /* Maximum inferred membank size is 512 bytes */ 108cbb45ff0SFrancisco Iglesias uint8_t stig_membank[512]; 109cbb45ff0SFrancisco Iglesias }; 110cbb45ff0SFrancisco Iglesias 11152581c71SMarkus Armbruster #endif /* XLNX_VERSAL_OSPI_H */ 112