1 #ifndef ALLWINNER_A10_PIT_H 2 #define ALLWINNER_A10_PIT_H 3 4 #include "hw/ptimer.h" 5 #include "hw/sysbus.h" 6 #include "qom/object.h" 7 8 #define TYPE_AW_A10_PIT "allwinner-A10-timer" 9 typedef struct AwA10PITState AwA10PITState; 10 DECLARE_INSTANCE_CHECKER(AwA10PITState, AW_A10_PIT, 11 TYPE_AW_A10_PIT) 12 13 #define AW_A10_PIT_TIMER_NR 6 14 #define AW_A10_PIT_TIMER_IRQ 0x1 15 #define AW_A10_PIT_WDOG_IRQ 0x100 16 17 #define AW_A10_PIT_TIMER_IRQ_EN 0 18 #define AW_A10_PIT_TIMER_IRQ_ST 0x4 19 20 #define AW_A10_PIT_TIMER_CONTROL 0x0 21 #define AW_A10_PIT_TIMER_EN 0x1 22 #define AW_A10_PIT_TIMER_RELOAD 0x2 23 #define AW_A10_PIT_TIMER_MODE 0x80 24 25 #define AW_A10_PIT_TIMER_INTERVAL 0x4 26 #define AW_A10_PIT_TIMER_COUNT 0x8 27 #define AW_A10_PIT_WDOG_CONTROL 0x90 28 #define AW_A10_PIT_WDOG_MODE 0x94 29 30 #define AW_A10_PIT_COUNT_CTL 0xa0 31 #define AW_A10_PIT_COUNT_RL_EN 0x2 32 #define AW_A10_PIT_COUNT_CLR_EN 0x1 33 #define AW_A10_PIT_COUNT_LO 0xa4 34 #define AW_A10_PIT_COUNT_HI 0xa8 35 36 #define AW_A10_PIT_TIMER_BASE 0x10 37 #define AW_A10_PIT_TIMER_BASE_END \ 38 (AW_A10_PIT_TIMER_BASE * 6 + AW_A10_PIT_TIMER_COUNT) 39 40 #define AW_A10_PIT_DEFAULT_CLOCK 0x4 41 42 43 typedef struct AwA10TimerContext { 44 AwA10PITState *container; 45 int index; 46 } AwA10TimerContext; 47 48 struct AwA10PITState { 49 /*< private >*/ 50 SysBusDevice parent_obj; 51 /*< public >*/ 52 qemu_irq irq[AW_A10_PIT_TIMER_NR]; 53 ptimer_state * timer[AW_A10_PIT_TIMER_NR]; 54 AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR]; 55 MemoryRegion iomem; 56 uint32_t clk_freq[4]; 57 58 uint32_t irq_enable; 59 uint32_t irq_status; 60 uint32_t control[AW_A10_PIT_TIMER_NR]; 61 uint32_t interval[AW_A10_PIT_TIMER_NR]; 62 uint32_t count[AW_A10_PIT_TIMER_NR]; 63 uint32_t watch_dog_mode; 64 uint32_t watch_dog_control; 65 uint32_t count_lo; 66 uint32_t count_hi; 67 uint32_t count_ctl; 68 }; 69 70 #endif 71