1 /* 2 * Virtio GPU Device 3 * 4 * Copyright Red Hat, Inc. 2013-2014 5 * 6 * Authors: 7 * Dave Airlie <airlied@redhat.com> 8 * Gerd Hoffmann <kraxel@redhat.com> 9 * 10 * This work is licensed under the terms of the GNU GPL, version 2. 11 * See the COPYING file in the top-level directory. 12 */ 13 14 #ifndef HW_VIRTIO_GPU_H 15 #define HW_VIRTIO_GPU_H 16 17 #include "qemu/queue.h" 18 #include "ui/qemu-pixman.h" 19 #include "ui/console.h" 20 #include "hw/virtio/virtio.h" 21 #include "qemu/log.h" 22 #include "sysemu/vhost-user-backend.h" 23 24 #include "standard-headers/linux/virtio_gpu.h" 25 #include "qom/object.h" 26 27 #define TYPE_VIRTIO_GPU_BASE "virtio-gpu-base" 28 OBJECT_DECLARE_TYPE(VirtIOGPUBase, VirtIOGPUBaseClass, 29 VIRTIO_GPU_BASE) 30 31 #define TYPE_VIRTIO_GPU "virtio-gpu-device" 32 OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPU, VIRTIO_GPU) 33 34 #define TYPE_VHOST_USER_GPU "vhost-user-gpu" 35 OBJECT_DECLARE_SIMPLE_TYPE(VhostUserGPU, VHOST_USER_GPU) 36 37 #define VIRTIO_ID_GPU 16 38 39 struct virtio_gpu_simple_resource { 40 uint32_t resource_id; 41 uint32_t width; 42 uint32_t height; 43 uint32_t format; 44 uint64_t *addrs; 45 struct iovec *iov; 46 unsigned int iov_cnt; 47 uint32_t scanout_bitmask; 48 pixman_image_t *image; 49 uint64_t hostmem; 50 QTAILQ_ENTRY(virtio_gpu_simple_resource) next; 51 }; 52 53 struct virtio_gpu_scanout { 54 QemuConsole *con; 55 DisplaySurface *ds; 56 uint32_t width, height; 57 int x, y; 58 int invalidate; 59 uint32_t resource_id; 60 struct virtio_gpu_update_cursor cursor; 61 QEMUCursor *current_cursor; 62 }; 63 64 struct virtio_gpu_requested_state { 65 uint32_t width, height; 66 int x, y; 67 }; 68 69 enum virtio_gpu_base_conf_flags { 70 VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1, 71 VIRTIO_GPU_FLAG_STATS_ENABLED, 72 VIRTIO_GPU_FLAG_EDID_ENABLED, 73 }; 74 75 #define virtio_gpu_virgl_enabled(_cfg) \ 76 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED)) 77 #define virtio_gpu_stats_enabled(_cfg) \ 78 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED)) 79 #define virtio_gpu_edid_enabled(_cfg) \ 80 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED)) 81 82 struct virtio_gpu_base_conf { 83 uint32_t max_outputs; 84 uint32_t flags; 85 uint32_t xres; 86 uint32_t yres; 87 }; 88 89 struct virtio_gpu_ctrl_command { 90 VirtQueueElement elem; 91 VirtQueue *vq; 92 struct virtio_gpu_ctrl_hdr cmd_hdr; 93 uint32_t error; 94 bool finished; 95 QTAILQ_ENTRY(virtio_gpu_ctrl_command) next; 96 }; 97 98 struct VirtIOGPUBase { 99 VirtIODevice parent_obj; 100 101 Error *migration_blocker; 102 103 struct virtio_gpu_base_conf conf; 104 struct virtio_gpu_config virtio_config; 105 const GraphicHwOps *hw_ops; 106 107 bool use_virgl_renderer; 108 int renderer_blocked; 109 int enable; 110 111 struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS]; 112 113 int enabled_output_bitmask; 114 struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS]; 115 }; 116 117 struct VirtIOGPUBaseClass { 118 VirtioDeviceClass parent; 119 120 void (*gl_unblock)(VirtIOGPUBase *g); 121 }; 122 123 #define VIRTIO_GPU_BASE_PROPERTIES(_state, _conf) \ 124 DEFINE_PROP_UINT32("max_outputs", _state, _conf.max_outputs, 1), \ 125 DEFINE_PROP_BIT("edid", _state, _conf.flags, \ 126 VIRTIO_GPU_FLAG_EDID_ENABLED, true), \ 127 DEFINE_PROP_UINT32("xres", _state, _conf.xres, 1024), \ 128 DEFINE_PROP_UINT32("yres", _state, _conf.yres, 768) 129 130 struct VirtIOGPU { 131 VirtIOGPUBase parent_obj; 132 133 uint64_t conf_max_hostmem; 134 135 VirtQueue *ctrl_vq; 136 VirtQueue *cursor_vq; 137 138 QEMUBH *ctrl_bh; 139 QEMUBH *cursor_bh; 140 141 QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist; 142 QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq; 143 QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq; 144 145 uint64_t hostmem; 146 147 bool renderer_inited; 148 bool renderer_reset; 149 QEMUTimer *fence_poll; 150 QEMUTimer *print_stats; 151 152 uint32_t inflight; 153 struct { 154 uint32_t max_inflight; 155 uint32_t requests; 156 uint32_t req_3d; 157 uint32_t bytes_3d; 158 } stats; 159 }; 160 161 struct VhostUserGPU { 162 VirtIOGPUBase parent_obj; 163 164 VhostUserBackend *vhost; 165 int vhost_gpu_fd; /* closed by the chardev */ 166 CharBackend vhost_chr; 167 QemuDmaBuf dmabuf[VIRTIO_GPU_MAX_SCANOUTS]; 168 bool backend_blocked; 169 }; 170 171 #define VIRTIO_GPU_FILL_CMD(out) do { \ 172 size_t s; \ 173 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \ 174 &out, sizeof(out)); \ 175 if (s != sizeof(out)) { \ 176 qemu_log_mask(LOG_GUEST_ERROR, \ 177 "%s: command size incorrect %zu vs %zu\n", \ 178 __func__, s, sizeof(out)); \ 179 return; \ 180 } \ 181 } while (0) 182 183 /* virtio-gpu-base.c */ 184 bool virtio_gpu_base_device_realize(DeviceState *qdev, 185 VirtIOHandleOutput ctrl_cb, 186 VirtIOHandleOutput cursor_cb, 187 Error **errp); 188 void virtio_gpu_base_reset(VirtIOGPUBase *g); 189 void virtio_gpu_base_fill_display_info(VirtIOGPUBase *g, 190 struct virtio_gpu_resp_display_info *dpy_info); 191 192 /* virtio-gpu.c */ 193 void virtio_gpu_ctrl_response(VirtIOGPU *g, 194 struct virtio_gpu_ctrl_command *cmd, 195 struct virtio_gpu_ctrl_hdr *resp, 196 size_t resp_len); 197 void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g, 198 struct virtio_gpu_ctrl_command *cmd, 199 enum virtio_gpu_ctrl_type type); 200 void virtio_gpu_get_display_info(VirtIOGPU *g, 201 struct virtio_gpu_ctrl_command *cmd); 202 void virtio_gpu_get_edid(VirtIOGPU *g, 203 struct virtio_gpu_ctrl_command *cmd); 204 int virtio_gpu_create_mapping_iov(VirtIOGPU *g, 205 struct virtio_gpu_resource_attach_backing *ab, 206 struct virtio_gpu_ctrl_command *cmd, 207 uint64_t **addr, struct iovec **iov); 208 void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g, 209 struct iovec *iov, uint32_t count); 210 void virtio_gpu_process_cmdq(VirtIOGPU *g); 211 212 /* virtio-gpu-3d.c */ 213 void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, 214 struct virtio_gpu_ctrl_command *cmd); 215 void virtio_gpu_virgl_fence_poll(VirtIOGPU *g); 216 void virtio_gpu_virgl_reset(VirtIOGPU *g); 217 int virtio_gpu_virgl_init(VirtIOGPU *g); 218 int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g); 219 220 #endif 221