1 /* 2 * Simple interface for atomic operations. 3 * 4 * Copyright (C) 2013 Red Hat, Inc. 5 * 6 * Author: Paolo Bonzini <pbonzini@redhat.com> 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 * See docs/devel/atomics.txt for discussion about the guarantees each 12 * atomic primitive is meant to provide. 13 */ 14 15 #ifndef QEMU_ATOMIC_H 16 #define QEMU_ATOMIC_H 17 18 /* Compiler barrier */ 19 #define barrier() ({ asm volatile("" ::: "memory"); (void)0; }) 20 21 /* The variable that receives the old value of an atomically-accessed 22 * variable must be non-qualified, because atomic builtins return values 23 * through a pointer-type argument as in __atomic_load(&var, &old, MODEL). 24 * 25 * This macro has to handle types smaller than int manually, because of 26 * implicit promotion. int and larger types, as well as pointers, can be 27 * converted to a non-qualified type just by applying a binary operator. 28 */ 29 #define typeof_strip_qual(expr) \ 30 typeof( \ 31 __builtin_choose_expr( \ 32 __builtin_types_compatible_p(typeof(expr), bool) || \ 33 __builtin_types_compatible_p(typeof(expr), const bool) || \ 34 __builtin_types_compatible_p(typeof(expr), volatile bool) || \ 35 __builtin_types_compatible_p(typeof(expr), const volatile bool), \ 36 (bool)1, \ 37 __builtin_choose_expr( \ 38 __builtin_types_compatible_p(typeof(expr), signed char) || \ 39 __builtin_types_compatible_p(typeof(expr), const signed char) || \ 40 __builtin_types_compatible_p(typeof(expr), volatile signed char) || \ 41 __builtin_types_compatible_p(typeof(expr), const volatile signed char), \ 42 (signed char)1, \ 43 __builtin_choose_expr( \ 44 __builtin_types_compatible_p(typeof(expr), unsigned char) || \ 45 __builtin_types_compatible_p(typeof(expr), const unsigned char) || \ 46 __builtin_types_compatible_p(typeof(expr), volatile unsigned char) || \ 47 __builtin_types_compatible_p(typeof(expr), const volatile unsigned char), \ 48 (unsigned char)1, \ 49 __builtin_choose_expr( \ 50 __builtin_types_compatible_p(typeof(expr), signed short) || \ 51 __builtin_types_compatible_p(typeof(expr), const signed short) || \ 52 __builtin_types_compatible_p(typeof(expr), volatile signed short) || \ 53 __builtin_types_compatible_p(typeof(expr), const volatile signed short), \ 54 (signed short)1, \ 55 __builtin_choose_expr( \ 56 __builtin_types_compatible_p(typeof(expr), unsigned short) || \ 57 __builtin_types_compatible_p(typeof(expr), const unsigned short) || \ 58 __builtin_types_compatible_p(typeof(expr), volatile unsigned short) || \ 59 __builtin_types_compatible_p(typeof(expr), const volatile unsigned short), \ 60 (unsigned short)1, \ 61 (expr)+0)))))) 62 63 #ifdef __ATOMIC_RELAXED 64 /* For C11 atomic ops */ 65 66 /* Manual memory barriers 67 * 68 *__atomic_thread_fence does not include a compiler barrier; instead, 69 * the barrier is part of __atomic_load/__atomic_store's "volatile-like" 70 * semantics. If smp_wmb() is a no-op, absence of the barrier means that 71 * the compiler is free to reorder stores on each side of the barrier. 72 * Add one here, and similarly in smp_rmb() and smp_read_barrier_depends(). 73 */ 74 75 #define smp_mb() ({ barrier(); __atomic_thread_fence(__ATOMIC_SEQ_CST); }) 76 #define smp_mb_release() ({ barrier(); __atomic_thread_fence(__ATOMIC_RELEASE); }) 77 #define smp_mb_acquire() ({ barrier(); __atomic_thread_fence(__ATOMIC_ACQUIRE); }) 78 79 /* Most compilers currently treat consume and acquire the same, but really 80 * no processors except Alpha need a barrier here. Leave it in if 81 * using Thread Sanitizer to avoid warnings, otherwise optimize it away. 82 */ 83 #if defined(__SANITIZE_THREAD__) 84 #define smp_read_barrier_depends() ({ barrier(); __atomic_thread_fence(__ATOMIC_CONSUME); }) 85 #elif defined(__alpha__) 86 #define smp_read_barrier_depends() asm volatile("mb":::"memory") 87 #else 88 #define smp_read_barrier_depends() barrier() 89 #endif 90 91 /* 92 * A signal barrier forces all pending local memory ops to be observed before 93 * a SIGSEGV is delivered to the *same* thread. In practice this is exactly 94 * the same as barrier(), but since we have the correct builtin, use it. 95 */ 96 #define signal_barrier() __atomic_signal_fence(__ATOMIC_SEQ_CST) 97 98 /* Sanity check that the size of an atomic operation isn't "overly large". 99 * Despite the fact that e.g. i686 has 64-bit atomic operations, we do not 100 * want to use them because we ought not need them, and this lets us do a 101 * bit of sanity checking that other 32-bit hosts might build. 102 * 103 * That said, we have a problem on 64-bit ILP32 hosts in that in order to 104 * sync with TCG_OVERSIZED_GUEST, this must match TCG_TARGET_REG_BITS. 105 * We'd prefer not want to pull in everything else TCG related, so handle 106 * those few cases by hand. 107 * 108 * Note that x32 is fully detected with __x86_64__ + _ILP32, and that for 109 * Sparc we always force the use of sparcv9 in configure. MIPS n32 (ILP32) & 110 * n64 (LP64) ABIs are both detected using __mips64. 111 */ 112 #if defined(__x86_64__) || defined(__sparc__) || defined(__mips64) 113 # define ATOMIC_REG_SIZE 8 114 #else 115 # define ATOMIC_REG_SIZE sizeof(void *) 116 #endif 117 118 /* Weak atomic operations prevent the compiler moving other 119 * loads/stores past the atomic operation load/store. However there is 120 * no explicit memory barrier for the processor. 121 * 122 * The C11 memory model says that variables that are accessed from 123 * different threads should at least be done with __ATOMIC_RELAXED 124 * primitives or the result is undefined. Generally this has little to 125 * no effect on the generated code but not using the atomic primitives 126 * will get flagged by sanitizers as a violation. 127 */ 128 #define qatomic_read__nocheck(ptr) \ 129 __atomic_load_n(ptr, __ATOMIC_RELAXED) 130 131 #define qatomic_read(ptr) \ 132 ({ \ 133 QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \ 134 qatomic_read__nocheck(ptr); \ 135 }) 136 137 #define qatomic_set__nocheck(ptr, i) \ 138 __atomic_store_n(ptr, i, __ATOMIC_RELAXED) 139 140 #define qatomic_set(ptr, i) do { \ 141 QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \ 142 qatomic_set__nocheck(ptr, i); \ 143 } while(0) 144 145 /* See above: most compilers currently treat consume and acquire the 146 * same, but this slows down qatomic_rcu_read unnecessarily. 147 */ 148 #ifdef __SANITIZE_THREAD__ 149 #define qatomic_rcu_read__nocheck(ptr, valptr) \ 150 __atomic_load(ptr, valptr, __ATOMIC_CONSUME); 151 #else 152 #define qatomic_rcu_read__nocheck(ptr, valptr) \ 153 __atomic_load(ptr, valptr, __ATOMIC_RELAXED); \ 154 smp_read_barrier_depends(); 155 #endif 156 157 #define qatomic_rcu_read(ptr) \ 158 ({ \ 159 QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \ 160 typeof_strip_qual(*ptr) _val; \ 161 qatomic_rcu_read__nocheck(ptr, &_val); \ 162 _val; \ 163 }) 164 165 #define qatomic_rcu_set(ptr, i) do { \ 166 QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \ 167 __atomic_store_n(ptr, i, __ATOMIC_RELEASE); \ 168 } while(0) 169 170 #define qatomic_load_acquire(ptr) \ 171 ({ \ 172 QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \ 173 typeof_strip_qual(*ptr) _val; \ 174 __atomic_load(ptr, &_val, __ATOMIC_ACQUIRE); \ 175 _val; \ 176 }) 177 178 #define qatomic_store_release(ptr, i) do { \ 179 QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \ 180 __atomic_store_n(ptr, i, __ATOMIC_RELEASE); \ 181 } while(0) 182 183 184 /* All the remaining operations are fully sequentially consistent */ 185 186 #define qatomic_xchg__nocheck(ptr, i) ({ \ 187 __atomic_exchange_n(ptr, (i), __ATOMIC_SEQ_CST); \ 188 }) 189 190 #define qatomic_xchg(ptr, i) ({ \ 191 QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \ 192 qatomic_xchg__nocheck(ptr, i); \ 193 }) 194 195 /* Returns the eventual value, failed or not */ 196 #define qatomic_cmpxchg__nocheck(ptr, old, new) ({ \ 197 typeof_strip_qual(*ptr) _old = (old); \ 198 (void)__atomic_compare_exchange_n(ptr, &_old, new, false, \ 199 __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); \ 200 _old; \ 201 }) 202 203 #define qatomic_cmpxchg(ptr, old, new) ({ \ 204 QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \ 205 qatomic_cmpxchg__nocheck(ptr, old, new); \ 206 }) 207 208 /* Provide shorter names for GCC atomic builtins, return old value */ 209 #define qatomic_fetch_inc(ptr) __atomic_fetch_add(ptr, 1, __ATOMIC_SEQ_CST) 210 #define qatomic_fetch_dec(ptr) __atomic_fetch_sub(ptr, 1, __ATOMIC_SEQ_CST) 211 212 #define qatomic_fetch_add(ptr, n) __atomic_fetch_add(ptr, n, __ATOMIC_SEQ_CST) 213 #define qatomic_fetch_sub(ptr, n) __atomic_fetch_sub(ptr, n, __ATOMIC_SEQ_CST) 214 #define qatomic_fetch_and(ptr, n) __atomic_fetch_and(ptr, n, __ATOMIC_SEQ_CST) 215 #define qatomic_fetch_or(ptr, n) __atomic_fetch_or(ptr, n, __ATOMIC_SEQ_CST) 216 #define qatomic_fetch_xor(ptr, n) __atomic_fetch_xor(ptr, n, __ATOMIC_SEQ_CST) 217 218 #define qatomic_inc_fetch(ptr) __atomic_add_fetch(ptr, 1, __ATOMIC_SEQ_CST) 219 #define qatomic_dec_fetch(ptr) __atomic_sub_fetch(ptr, 1, __ATOMIC_SEQ_CST) 220 #define qatomic_add_fetch(ptr, n) __atomic_add_fetch(ptr, n, __ATOMIC_SEQ_CST) 221 #define qatomic_sub_fetch(ptr, n) __atomic_sub_fetch(ptr, n, __ATOMIC_SEQ_CST) 222 #define qatomic_and_fetch(ptr, n) __atomic_and_fetch(ptr, n, __ATOMIC_SEQ_CST) 223 #define qatomic_or_fetch(ptr, n) __atomic_or_fetch(ptr, n, __ATOMIC_SEQ_CST) 224 #define qatomic_xor_fetch(ptr, n) __atomic_xor_fetch(ptr, n, __ATOMIC_SEQ_CST) 225 226 /* And even shorter names that return void. */ 227 #define qatomic_inc(ptr) \ 228 ((void) __atomic_fetch_add(ptr, 1, __ATOMIC_SEQ_CST)) 229 #define qatomic_dec(ptr) \ 230 ((void) __atomic_fetch_sub(ptr, 1, __ATOMIC_SEQ_CST)) 231 #define qatomic_add(ptr, n) \ 232 ((void) __atomic_fetch_add(ptr, n, __ATOMIC_SEQ_CST)) 233 #define qatomic_sub(ptr, n) \ 234 ((void) __atomic_fetch_sub(ptr, n, __ATOMIC_SEQ_CST)) 235 #define qatomic_and(ptr, n) \ 236 ((void) __atomic_fetch_and(ptr, n, __ATOMIC_SEQ_CST)) 237 #define qatomic_or(ptr, n) \ 238 ((void) __atomic_fetch_or(ptr, n, __ATOMIC_SEQ_CST)) 239 #define qatomic_xor(ptr, n) \ 240 ((void) __atomic_fetch_xor(ptr, n, __ATOMIC_SEQ_CST)) 241 242 #else /* __ATOMIC_RELAXED */ 243 244 /* 245 * We use GCC builtin if it's available, as that can use mfence on 246 * 32-bit as well, e.g. if built with -march=pentium-m. However, on 247 * i386 the spec is buggy, and the implementation followed it until 248 * 4.3 (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793). 249 */ 250 #if defined(__i386__) || defined(__x86_64__) 251 #if !QEMU_GNUC_PREREQ(4, 4) 252 #if defined __x86_64__ 253 #define smp_mb() ({ asm volatile("mfence" ::: "memory"); (void)0; }) 254 #else 255 #define smp_mb() ({ asm volatile("lock; addl $0,0(%%esp) " ::: "memory"); (void)0; }) 256 #endif 257 #endif 258 #endif 259 260 261 #ifdef __alpha__ 262 #define smp_read_barrier_depends() asm volatile("mb":::"memory") 263 #endif 264 265 #if defined(__i386__) || defined(__x86_64__) || defined(__s390x__) 266 267 /* 268 * Because of the strongly ordered storage model, wmb() and rmb() are nops 269 * here (a compiler barrier only). QEMU doesn't do accesses to write-combining 270 * qemu memory or non-temporal load/stores from C code. 271 */ 272 #define smp_mb_release() barrier() 273 #define smp_mb_acquire() barrier() 274 275 /* 276 * __sync_lock_test_and_set() is documented to be an acquire barrier only, 277 * but it is a full barrier at the hardware level. Add a compiler barrier 278 * to make it a full barrier also at the compiler level. 279 */ 280 #define qatomic_xchg(ptr, i) (barrier(), __sync_lock_test_and_set(ptr, i)) 281 282 #elif defined(_ARCH_PPC) 283 284 /* 285 * We use an eieio() for wmb() on powerpc. This assumes we don't 286 * need to order cacheable and non-cacheable stores with respect to 287 * each other. 288 * 289 * smp_mb has the same problem as on x86 for not-very-new GCC 290 * (http://patchwork.ozlabs.org/patch/126184/, Nov 2011). 291 */ 292 #define smp_wmb() ({ asm volatile("eieio" ::: "memory"); (void)0; }) 293 #if defined(__powerpc64__) 294 #define smp_mb_release() ({ asm volatile("lwsync" ::: "memory"); (void)0; }) 295 #define smp_mb_acquire() ({ asm volatile("lwsync" ::: "memory"); (void)0; }) 296 #else 297 #define smp_mb_release() ({ asm volatile("sync" ::: "memory"); (void)0; }) 298 #define smp_mb_acquire() ({ asm volatile("sync" ::: "memory"); (void)0; }) 299 #endif 300 #define smp_mb() ({ asm volatile("sync" ::: "memory"); (void)0; }) 301 302 #endif /* _ARCH_PPC */ 303 304 /* 305 * For (host) platforms we don't have explicit barrier definitions 306 * for, we use the gcc __sync_synchronize() primitive to generate a 307 * full barrier. This should be safe on all platforms, though it may 308 * be overkill for smp_mb_acquire() and smp_mb_release(). 309 */ 310 #ifndef smp_mb 311 #define smp_mb() __sync_synchronize() 312 #endif 313 314 #ifndef smp_mb_acquire 315 #define smp_mb_acquire() __sync_synchronize() 316 #endif 317 318 #ifndef smp_mb_release 319 #define smp_mb_release() __sync_synchronize() 320 #endif 321 322 #ifndef smp_read_barrier_depends 323 #define smp_read_barrier_depends() barrier() 324 #endif 325 326 #ifndef signal_barrier 327 #define signal_barrier() barrier() 328 #endif 329 330 /* These will only be atomic if the processor does the fetch or store 331 * in a single issue memory operation 332 */ 333 #define qatomic_read__nocheck(p) (*(__typeof__(*(p)) volatile*) (p)) 334 #define qatomic_set__nocheck(p, i) ((*(__typeof__(*(p)) volatile*) (p)) = (i)) 335 336 #define qatomic_read(ptr) qatomic_read__nocheck(ptr) 337 #define qatomic_set(ptr, i) qatomic_set__nocheck(ptr,i) 338 339 /** 340 * qatomic_rcu_read - reads a RCU-protected pointer to a local variable 341 * into a RCU read-side critical section. The pointer can later be safely 342 * dereferenced within the critical section. 343 * 344 * This ensures that the pointer copy is invariant thorough the whole critical 345 * section. 346 * 347 * Inserts memory barriers on architectures that require them (currently only 348 * Alpha) and documents which pointers are protected by RCU. 349 * 350 * qatomic_rcu_read also includes a compiler barrier to ensure that 351 * value-speculative optimizations (e.g. VSS: Value Speculation 352 * Scheduling) does not perform the data read before the pointer read 353 * by speculating the value of the pointer. 354 * 355 * Should match qatomic_rcu_set(), qatomic_xchg(), qatomic_cmpxchg(). 356 */ 357 #define qatomic_rcu_read(ptr) ({ \ 358 typeof(*ptr) _val = qatomic_read(ptr); \ 359 smp_read_barrier_depends(); \ 360 _val; \ 361 }) 362 363 /** 364 * qatomic_rcu_set - assigns (publicizes) a pointer to a new data structure 365 * meant to be read by RCU read-side critical sections. 366 * 367 * Documents which pointers will be dereferenced by RCU read-side critical 368 * sections and adds the required memory barriers on architectures requiring 369 * them. It also makes sure the compiler does not reorder code initializing the 370 * data structure before its publication. 371 * 372 * Should match qatomic_rcu_read(). 373 */ 374 #define qatomic_rcu_set(ptr, i) do { \ 375 smp_wmb(); \ 376 qatomic_set(ptr, i); \ 377 } while (0) 378 379 #define qatomic_load_acquire(ptr) ({ \ 380 typeof(*ptr) _val = qatomic_read(ptr); \ 381 smp_mb_acquire(); \ 382 _val; \ 383 }) 384 385 #define qatomic_store_release(ptr, i) do { \ 386 smp_mb_release(); \ 387 qatomic_set(ptr, i); \ 388 } while (0) 389 390 #ifndef qatomic_xchg 391 #if defined(__clang__) 392 #define qatomic_xchg(ptr, i) __sync_swap(ptr, i) 393 #else 394 /* __sync_lock_test_and_set() is documented to be an acquire barrier only. */ 395 #define qatomic_xchg(ptr, i) (smp_mb(), __sync_lock_test_and_set(ptr, i)) 396 #endif 397 #endif 398 #define qatomic_xchg__nocheck qatomic_xchg 399 400 /* Provide shorter names for GCC atomic builtins. */ 401 #define qatomic_fetch_inc(ptr) __sync_fetch_and_add(ptr, 1) 402 #define qatomic_fetch_dec(ptr) __sync_fetch_and_add(ptr, -1) 403 404 #define qatomic_fetch_add(ptr, n) __sync_fetch_and_add(ptr, n) 405 #define qatomic_fetch_sub(ptr, n) __sync_fetch_and_sub(ptr, n) 406 #define qatomic_fetch_and(ptr, n) __sync_fetch_and_and(ptr, n) 407 #define qatomic_fetch_or(ptr, n) __sync_fetch_and_or(ptr, n) 408 #define qatomic_fetch_xor(ptr, n) __sync_fetch_and_xor(ptr, n) 409 410 #define qatomic_inc_fetch(ptr) __sync_add_and_fetch(ptr, 1) 411 #define qatomic_dec_fetch(ptr) __sync_add_and_fetch(ptr, -1) 412 #define qatomic_add_fetch(ptr, n) __sync_add_and_fetch(ptr, n) 413 #define qatomic_sub_fetch(ptr, n) __sync_sub_and_fetch(ptr, n) 414 #define qatomic_and_fetch(ptr, n) __sync_and_and_fetch(ptr, n) 415 #define qatomic_or_fetch(ptr, n) __sync_or_and_fetch(ptr, n) 416 #define qatomic_xor_fetch(ptr, n) __sync_xor_and_fetch(ptr, n) 417 418 #define qatomic_cmpxchg(ptr, old, new) \ 419 __sync_val_compare_and_swap(ptr, old, new) 420 #define qatomic_cmpxchg__nocheck(ptr, old, new) qatomic_cmpxchg(ptr, old, new) 421 422 /* And even shorter names that return void. */ 423 #define qatomic_inc(ptr) ((void) __sync_fetch_and_add(ptr, 1)) 424 #define qatomic_dec(ptr) ((void) __sync_fetch_and_add(ptr, -1)) 425 #define qatomic_add(ptr, n) ((void) __sync_fetch_and_add(ptr, n)) 426 #define qatomic_sub(ptr, n) ((void) __sync_fetch_and_sub(ptr, n)) 427 #define qatomic_and(ptr, n) ((void) __sync_fetch_and_and(ptr, n)) 428 #define qatomic_or(ptr, n) ((void) __sync_fetch_and_or(ptr, n)) 429 #define qatomic_xor(ptr, n) ((void) __sync_fetch_and_xor(ptr, n)) 430 431 #endif /* __ATOMIC_RELAXED */ 432 433 #ifndef smp_wmb 434 #define smp_wmb() smp_mb_release() 435 #endif 436 #ifndef smp_rmb 437 #define smp_rmb() smp_mb_acquire() 438 #endif 439 440 /* This is more efficient than a store plus a fence. */ 441 #if !defined(__SANITIZE_THREAD__) 442 #if defined(__i386__) || defined(__x86_64__) || defined(__s390x__) 443 #define qatomic_mb_set(ptr, i) ((void)qatomic_xchg(ptr, i)) 444 #endif 445 #endif 446 447 /* qatomic_mb_read/set semantics map Java volatile variables. They are 448 * less expensive on some platforms (notably POWER) than fully 449 * sequentially consistent operations. 450 * 451 * As long as they are used as paired operations they are safe to 452 * use. See docs/devel/atomics.txt for more discussion. 453 */ 454 455 #ifndef qatomic_mb_read 456 #define qatomic_mb_read(ptr) \ 457 qatomic_load_acquire(ptr) 458 #endif 459 460 #ifndef qatomic_mb_set 461 #define qatomic_mb_set(ptr, i) do { \ 462 qatomic_store_release(ptr, i); \ 463 smp_mb(); \ 464 } while(0) 465 #endif 466 467 #define qatomic_fetch_inc_nonzero(ptr) ({ \ 468 typeof_strip_qual(*ptr) _oldn = qatomic_read(ptr); \ 469 while (_oldn && qatomic_cmpxchg(ptr, _oldn, _oldn + 1) != _oldn) { \ 470 _oldn = qatomic_read(ptr); \ 471 } \ 472 _oldn; \ 473 }) 474 475 /* Abstractions to access atomically (i.e. "once") i64/u64 variables */ 476 #ifdef CONFIG_ATOMIC64 477 static inline int64_t qatomic_read_i64(const int64_t *ptr) 478 { 479 /* use __nocheck because sizeof(void *) might be < sizeof(u64) */ 480 return qatomic_read__nocheck(ptr); 481 } 482 483 static inline uint64_t qatomic_read_u64(const uint64_t *ptr) 484 { 485 return qatomic_read__nocheck(ptr); 486 } 487 488 static inline void qatomic_set_i64(int64_t *ptr, int64_t val) 489 { 490 qatomic_set__nocheck(ptr, val); 491 } 492 493 static inline void qatomic_set_u64(uint64_t *ptr, uint64_t val) 494 { 495 qatomic_set__nocheck(ptr, val); 496 } 497 498 static inline void qatomic64_init(void) 499 { 500 } 501 #else /* !CONFIG_ATOMIC64 */ 502 int64_t qatomic_read_i64(const int64_t *ptr); 503 uint64_t qatomic_read_u64(const uint64_t *ptr); 504 void qatomic_set_i64(int64_t *ptr, int64_t val); 505 void qatomic_set_u64(uint64_t *ptr, uint64_t val); 506 void qatomic64_init(void); 507 #endif /* !CONFIG_ATOMIC64 */ 508 509 #endif /* QEMU_ATOMIC_H */ 510