1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 28 #if defined(__cplusplus) 29 extern "C" { 30 #endif 31 32 /** 33 * DOC: overview 34 * 35 * In the DRM subsystem, framebuffer pixel formats are described using the 36 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 37 * fourcc code, a Format Modifier may optionally be provided, in order to 38 * further describe the buffer's format - for example tiling or compression. 39 * 40 * Format Modifiers 41 * ---------------- 42 * 43 * Format modifiers are used in conjunction with a fourcc code, forming a 44 * unique fourcc:modifier pair. This format:modifier pair must fully define the 45 * format and data layout of the buffer, and should be the only way to describe 46 * that particular buffer. 47 * 48 * Having multiple fourcc:modifier pairs which describe the same layout should 49 * be avoided, as such aliases run the risk of different drivers exposing 50 * different names for the same data format, forcing userspace to understand 51 * that they are aliases. 52 * 53 * Format modifiers may change any property of the buffer, including the number 54 * of planes and/or the required allocation size. Format modifiers are 55 * vendor-namespaced, and as such the relationship between a fourcc code and a 56 * modifier is specific to the modifer being used. For example, some modifiers 57 * may preserve meaning - such as number of planes - from the fourcc code, 58 * whereas others may not. 59 * 60 * Modifiers must uniquely encode buffer layout. In other words, a buffer must 61 * match only a single modifier. A modifier must not be a subset of layouts of 62 * another modifier. For instance, it's incorrect to encode pitch alignment in 63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel 64 * aligned modifier. That said, modifiers can have implicit minimal 65 * requirements. 66 * 67 * For modifiers where the combination of fourcc code and modifier can alias, 68 * a canonical pair needs to be defined and used by all drivers. Preferred 69 * combinations are also encouraged where all combinations might lead to 70 * confusion and unnecessarily reduced interoperability. An example for the 71 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. 72 * 73 * There are two kinds of modifier users: 74 * 75 * - Kernel and user-space drivers: for drivers it's important that modifiers 76 * don't alias, otherwise two drivers might support the same format but use 77 * different aliases, preventing them from sharing buffers in an efficient 78 * format. 79 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users 80 * see modifiers as opaque tokens they can check for equality and intersect. 81 * These users musn't need to know to reason about the modifier value 82 * (i.e. they are not expected to extract information out of the modifier). 83 * 84 * Vendors should document their modifier usage in as much detail as 85 * possible, to ensure maximum compatibility across devices, drivers and 86 * applications. 87 * 88 * The authoritative list of format modifier codes is found in 89 * `include/uapi/drm/drm_fourcc.h` 90 */ 91 92 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ 93 ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) 94 95 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ 96 97 /* Reserve 0 for the invalid format specifier */ 98 #define DRM_FORMAT_INVALID 0 99 100 /* color index */ 101 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 102 103 /* 8 bpp Red */ 104 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 105 106 /* 16 bpp Red */ 107 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 108 109 /* 16 bpp RG */ 110 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 111 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 112 113 /* 32 bpp RG */ 114 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 115 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 116 117 /* 8 bpp RGB */ 118 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 119 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 120 121 /* 16 bpp RGB */ 122 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 123 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 124 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 125 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 126 127 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 128 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 129 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 130 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 131 132 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 133 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 134 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 135 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 136 137 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 138 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 139 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 140 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 141 142 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 143 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 144 145 /* 24 bpp RGB */ 146 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 147 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 148 149 /* 32 bpp RGB */ 150 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 151 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 152 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 153 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 154 155 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 156 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 157 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 158 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 159 160 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 161 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 162 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 163 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 164 165 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 166 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 167 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 168 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 169 170 /* 171 * Floating point 64bpp RGB 172 * IEEE 754-2008 binary16 half-precision float 173 * [15:0] sign:exponent:mantissa 1:5:10 174 */ 175 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 176 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 177 178 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 179 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 180 181 /* 182 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits 183 * of unused padding per component: 184 */ 185 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ 186 187 /* packed YCbCr */ 188 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 189 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 190 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 191 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 192 193 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 194 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 195 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ 196 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ 197 198 /* 199 * packed Y2xx indicate for each component, xx valid data occupy msb 200 * 16-xx padding occupy lsb 201 */ 202 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ 203 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ 204 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ 205 206 /* 207 * packed Y4xx indicate for each component, xx valid data occupy msb 208 * 16-xx padding occupy lsb except Y410 209 */ 210 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ 211 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 212 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ 213 214 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ 215 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 216 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ 217 218 /* 219 * packed YCbCr420 2x2 tiled formats 220 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 221 */ 222 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 223 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 224 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 225 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 226 227 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 228 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 229 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 230 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 231 232 /* 233 * 1-plane YUV 4:2:0 234 * In these formats, the component ordering is specified (Y, followed by U 235 * then V), but the exact Linear layout is undefined. 236 * These formats can only be used with a non-Linear modifier. 237 */ 238 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') 239 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') 240 241 /* 242 * 2 plane RGB + A 243 * index 0 = RGB plane, same format as the corresponding non _A8 format has 244 * index 1 = A plane, [7:0] A 245 */ 246 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 247 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 248 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 249 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 250 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 251 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 252 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 253 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 254 255 /* 256 * 2 plane YCbCr 257 * index 0 = Y plane, [7:0] Y 258 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 259 * or 260 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 261 */ 262 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 263 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 264 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 265 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 266 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 267 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 268 /* 269 * 2 plane YCbCr 270 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian 271 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian 272 */ 273 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ 274 275 /* 276 * 2 plane YCbCr MSB aligned 277 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 278 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 279 */ 280 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ 281 282 /* 283 * 2 plane YCbCr MSB aligned 284 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 285 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 286 */ 287 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ 288 289 /* 290 * 2 plane YCbCr MSB aligned 291 * index 0 = Y plane, [15:0] Y:x [12:4] little endian 292 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian 293 */ 294 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ 295 296 /* 297 * 2 plane YCbCr MSB aligned 298 * index 0 = Y plane, [15:0] Y little endian 299 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian 300 */ 301 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ 302 303 /* 3 plane non-subsampled (444) YCbCr 304 * 16 bits per component, but only 10 bits are used and 6 bits are padded 305 * index 0: Y plane, [15:0] Y:x [10:6] little endian 306 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian 307 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian 308 */ 309 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') 310 311 /* 3 plane non-subsampled (444) YCrCb 312 * 16 bits per component, but only 10 bits are used and 6 bits are padded 313 * index 0: Y plane, [15:0] Y:x [10:6] little endian 314 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian 315 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian 316 */ 317 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') 318 319 /* 320 * 3 plane YCbCr 321 * index 0: Y plane, [7:0] Y 322 * index 1: Cb plane, [7:0] Cb 323 * index 2: Cr plane, [7:0] Cr 324 * or 325 * index 1: Cr plane, [7:0] Cr 326 * index 2: Cb plane, [7:0] Cb 327 */ 328 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 329 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 330 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 331 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 332 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 333 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 334 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 335 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 336 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 337 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 338 339 340 /* 341 * Format Modifiers: 342 * 343 * Format modifiers describe, typically, a re-ordering or modification 344 * of the data in a plane of an FB. This can be used to express tiled/ 345 * swizzled formats, or compression, or a combination of the two. 346 * 347 * The upper 8 bits of the format modifier are a vendor-id as assigned 348 * below. The lower 56 bits are assigned as vendor sees fit. 349 */ 350 351 /* Vendor Ids: */ 352 #define DRM_FORMAT_MOD_VENDOR_NONE 0 353 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 354 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 355 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 356 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 357 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 358 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 359 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 360 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 361 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 362 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a 363 364 /* add more to the end as needed */ 365 366 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 367 368 #define fourcc_mod_code(vendor, val) \ 369 ((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 370 371 /* 372 * Format Modifier tokens: 373 * 374 * When adding a new token please document the layout with a code comment, 375 * similar to the fourcc codes above. drm_fourcc.h is considered the 376 * authoritative source for all of these. 377 * 378 * Generic modifier names: 379 * 380 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names 381 * for layouts which are common across multiple vendors. To preserve 382 * compatibility, in cases where a vendor-specific definition already exists and 383 * a generic name for it is desired, the common name is a purely symbolic alias 384 * and must use the same numerical value as the original definition. 385 * 386 * Note that generic names should only be used for modifiers which describe 387 * generic layouts (such as pixel re-ordering), which may have 388 * independently-developed support across multiple vendors. 389 * 390 * In future cases where a generic layout is identified before merging with a 391 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor 392 * 'NONE' could be considered. This should only be for obvious, exceptional 393 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only 394 * apply to a single vendor. 395 * 396 * Generic names should not be used for cases where multiple hardware vendors 397 * have implementations of the same standardised compression scheme (such as 398 * AFBC). In those cases, all implementations should use the same format 399 * modifier(s), reflecting the vendor of the standard. 400 */ 401 402 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE 403 404 /* 405 * Invalid Modifier 406 * 407 * This modifier can be used as a sentinel to terminate the format modifiers 408 * list, or to initialize a variable with an invalid modifier. It might also be 409 * used to report an error back to userspace for certain APIs. 410 */ 411 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 412 413 /* 414 * Linear Layout 415 * 416 * Just plain linear layout. Note that this is different from no specifying any 417 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 418 * which tells the driver to also take driver-internal information into account 419 * and so might actually result in a tiled framebuffer. 420 */ 421 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 422 423 /* 424 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead 425 * 426 * The "none" format modifier doesn't actually mean that the modifier is 427 * implicit, instead it means that the layout is linear. Whether modifiers are 428 * used is out-of-band information carried in an API-specific way (e.g. in a 429 * flag for drm_mode_fb_cmd2). 430 */ 431 #define DRM_FORMAT_MOD_NONE 0 432 433 /* Intel framebuffer modifiers */ 434 435 /* 436 * Intel X-tiling layout 437 * 438 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 439 * in row-major layout. Within the tile bytes are laid out row-major, with 440 * a platform-dependent stride. On top of that the memory can apply 441 * platform-depending swizzling of some higher address bits into bit6. 442 * 443 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 444 * On earlier platforms the is highly platforms specific and not useful for 445 * cross-driver sharing. It exists since on a given platform it does uniquely 446 * identify the layout in a simple way for i915-specific userspace, which 447 * facilitated conversion of userspace to modifiers. Additionally the exact 448 * format on some really old platforms is not known. 449 */ 450 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 451 452 /* 453 * Intel Y-tiling layout 454 * 455 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 456 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 457 * chunks column-major, with a platform-dependent height. On top of that the 458 * memory can apply platform-depending swizzling of some higher address bits 459 * into bit6. 460 * 461 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 462 * On earlier platforms the is highly platforms specific and not useful for 463 * cross-driver sharing. It exists since on a given platform it does uniquely 464 * identify the layout in a simple way for i915-specific userspace, which 465 * facilitated conversion of userspace to modifiers. Additionally the exact 466 * format on some really old platforms is not known. 467 */ 468 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 469 470 /* 471 * Intel Yf-tiling layout 472 * 473 * This is a tiled layout using 4Kb tiles in row-major layout. 474 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 475 * are arranged in four groups (two wide, two high) with column-major layout. 476 * Each group therefore consits out of four 256 byte units, which are also laid 477 * out as 2x2 column-major. 478 * 256 byte units are made out of four 64 byte blocks of pixels, producing 479 * either a square block or a 2:1 unit. 480 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 481 * in pixel depends on the pixel depth. 482 */ 483 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 484 485 /* 486 * Intel color control surface (CCS) for render compression 487 * 488 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 489 * The main surface will be plane index 0 and must be Y/Yf-tiled, 490 * the CCS will be plane index 1. 491 * 492 * Each CCS tile matches a 1024x512 pixel area of the main surface. 493 * To match certain aspects of the 3D hardware the CCS is 494 * considered to be made up of normal 128Bx32 Y tiles, Thus 495 * the CCS pitch must be specified in multiples of 128 bytes. 496 * 497 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 498 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 499 * But that fact is not relevant unless the memory is accessed 500 * directly. 501 */ 502 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 503 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 504 505 /* 506 * Intel color control surfaces (CCS) for Gen-12 render compression. 507 * 508 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 509 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 510 * main surface. In other words, 4 bits in CCS map to a main surface cache 511 * line pair. The main surface pitch is required to be a multiple of four 512 * Y-tile widths. 513 */ 514 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) 515 516 /* 517 * Intel color control surfaces (CCS) for Gen-12 media compression 518 * 519 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 520 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 521 * main surface. In other words, 4 bits in CCS map to a main surface cache 522 * line pair. The main surface pitch is required to be a multiple of four 523 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the 524 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 525 * planes 2 and 3 for the respective CCS. 526 */ 527 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) 528 529 /* 530 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 531 * 532 * Macroblocks are laid in a Z-shape, and each pixel data is following the 533 * standard NV12 style. 534 * As for NV12, an image is the result of two frame buffers: one for Y, 535 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 536 * Alignment requirements are (for each buffer): 537 * - multiple of 128 pixels for the width 538 * - multiple of 32 pixels for the height 539 * 540 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 541 */ 542 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 543 544 /* 545 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 546 * 547 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 548 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 549 * they correspond to their 16x16 luma block. 550 */ 551 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 552 553 /* 554 * Qualcomm Compressed Format 555 * 556 * Refers to a compressed variant of the base format that is compressed. 557 * Implementation may be platform and base-format specific. 558 * 559 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 560 * Pixel data pitch/stride is aligned with macrotile width. 561 * Pixel data height is aligned with macrotile height. 562 * Entire pixel data buffer is aligned with 4k(bytes). 563 */ 564 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 565 566 /* Vivante framebuffer modifiers */ 567 568 /* 569 * Vivante 4x4 tiling layout 570 * 571 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 572 * layout. 573 */ 574 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 575 576 /* 577 * Vivante 64x64 super-tiling layout 578 * 579 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 580 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 581 * major layout. 582 * 583 * For more information: see 584 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 585 */ 586 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 587 588 /* 589 * Vivante 4x4 tiling layout for dual-pipe 590 * 591 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 592 * different base address. Offsets from the base addresses are therefore halved 593 * compared to the non-split tiled layout. 594 */ 595 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 596 597 /* 598 * Vivante 64x64 super-tiling layout for dual-pipe 599 * 600 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 601 * starts at a different base address. Offsets from the base addresses are 602 * therefore halved compared to the non-split super-tiled layout. 603 */ 604 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 605 606 /* NVIDIA frame buffer modifiers */ 607 608 /* 609 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 610 * 611 * Pixels are arranged in simple tiles of 16 x 16 bytes. 612 */ 613 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 614 615 /* 616 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, 617 * and Tegra GPUs starting with Tegra K1. 618 * 619 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies 620 * based on the architecture generation. GOBs themselves are then arranged in 621 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power 622 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents 623 * a block depth or height of "4"). 624 * 625 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 626 * in full detail. 627 * 628 * Macro 629 * Bits Param Description 630 * ---- ----- ----------------------------------------------------------------- 631 * 632 * 3:0 h log2(height) of each block, in GOBs. Placed here for 633 * compatibility with the existing 634 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 635 * 636 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for 637 * compatibility with the existing 638 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 639 * 640 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block 641 * size). Must be zero. 642 * 643 * Note there is no log2(width) parameter. Some portions of the 644 * hardware support a block width of two gobs, but it is impractical 645 * to use due to lack of support elsewhere, and has no known 646 * benefits. 647 * 648 * 11:9 - Reserved (To support 2D-array textures with variable array stride 649 * in blocks, specified via log2(tile width in blocks)). Must be 650 * zero. 651 * 652 * 19:12 k Page Kind. This value directly maps to a field in the page 653 * tables of all GPUs >= NV50. It affects the exact layout of bits 654 * in memory and can be derived from the tuple 655 * 656 * (format, GPU model, compression type, samples per pixel) 657 * 658 * Where compression type is defined below. If GPU model were 659 * implied by the format modifier, format, or memory buffer, page 660 * kind would not need to be included in the modifier itself, but 661 * since the modifier should define the layout of the associated 662 * memory buffer independent from any device or other context, it 663 * must be included here. 664 * 665 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed 666 * starting with Fermi GPUs. Additionally, the mapping between page 667 * kind and bit layout has changed at various points. 668 * 669 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping 670 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping 671 * 2 = Gob Height 8, Turing+ Page Kind mapping 672 * 3 = Reserved for future use. 673 * 674 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 675 * bit remapping step that occurs at an even lower level than the 676 * page kind and block linear swizzles. This causes the layout of 677 * surfaces mapped in those SOC's GPUs to be incompatible with the 678 * equivalent mapping on other GPUs in the same system. 679 * 680 * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 681 * 1 = Desktop GPU and Tegra Xavier+ Layout 682 * 683 * 25:23 c Lossless Framebuffer Compression type. 684 * 685 * 0 = none 686 * 1 = ROP/3D, layout 1, exact compression format implied by Page 687 * Kind field 688 * 2 = ROP/3D, layout 2, exact compression format implied by Page 689 * Kind field 690 * 3 = CDE horizontal 691 * 4 = CDE vertical 692 * 5 = Reserved for future use 693 * 6 = Reserved for future use 694 * 7 = Reserved for future use 695 * 696 * 55:25 - Reserved for future use. Must be zero. 697 */ 698 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 699 fourcc_mod_code(NVIDIA, (0x10 | \ 700 ((h) & 0xf) | \ 701 (((k) & 0xff) << 12) | \ 702 (((g) & 0x3) << 20) | \ 703 (((s) & 0x1) << 22) | \ 704 (((c) & 0x7) << 23))) 705 706 /* To grandfather in prior block linear format modifiers to the above layout, 707 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable 708 * with block-linear layouts, is remapped within drivers to the value 0xfe, 709 * which corresponds to the "generic" kind used for simple single-sample 710 * uncompressed color formats on Fermi - Volta GPUs. 711 */ 712 static inline uint64_t 713 drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier) 714 { 715 if (!(modifier & 0x10) || (modifier & (0xff << 12))) 716 return modifier; 717 else 718 return modifier | (0xfe << 12); 719 } 720 721 /* 722 * 16Bx2 Block Linear layout, used by Tegra K1 and later 723 * 724 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 725 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 726 * 727 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 728 * 729 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 730 * Valid values are: 731 * 732 * 0 == ONE_GOB 733 * 1 == TWO_GOBS 734 * 2 == FOUR_GOBS 735 * 3 == EIGHT_GOBS 736 * 4 == SIXTEEN_GOBS 737 * 5 == THIRTYTWO_GOBS 738 * 739 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 740 * in full detail. 741 */ 742 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 743 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) 744 745 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 746 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) 747 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 748 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) 749 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 750 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) 751 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 752 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) 753 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 754 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) 755 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 756 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) 757 758 /* 759 * Some Broadcom modifiers take parameters, for example the number of 760 * vertical lines in the image. Reserve the lower 32 bits for modifier 761 * type, and the next 24 bits for parameters. Top 8 bits are the 762 * vendor code. 763 */ 764 #define __fourcc_mod_broadcom_param_shift 8 765 #define __fourcc_mod_broadcom_param_bits 48 766 #define fourcc_mod_broadcom_code(val, params) \ 767 fourcc_mod_code(BROADCOM, ((((uint64_t)params) << __fourcc_mod_broadcom_param_shift) | val)) 768 #define fourcc_mod_broadcom_param(m) \ 769 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 770 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 771 #define fourcc_mod_broadcom_mod(m) \ 772 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 773 __fourcc_mod_broadcom_param_shift)) 774 775 /* 776 * Broadcom VC4 "T" format 777 * 778 * This is the primary layout that the V3D GPU can texture from (it 779 * can't do linear). The T format has: 780 * 781 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 782 * pixels at 32 bit depth. 783 * 784 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 785 * 16x16 pixels). 786 * 787 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 788 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 789 * they're (TR, BR, BL, TL), where bottom left is start of memory. 790 * 791 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 792 * tiles) or right-to-left (odd rows of 4k tiles). 793 */ 794 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 795 796 /* 797 * Broadcom SAND format 798 * 799 * This is the native format that the H.264 codec block uses. For VC4 800 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 801 * 802 * The image can be considered to be split into columns, and the 803 * columns are placed consecutively into memory. The width of those 804 * columns can be either 32, 64, 128, or 256 pixels, but in practice 805 * only 128 pixel columns are used. 806 * 807 * The pitch between the start of each column is set to optimally 808 * switch between SDRAM banks. This is passed as the number of lines 809 * of column width in the modifier (we can't use the stride value due 810 * to various core checks that look at it , so you should set the 811 * stride to width*cpp). 812 * 813 * Note that the column height for this format modifier is the same 814 * for all of the planes, assuming that each column contains both Y 815 * and UV. Some SAND-using hardware stores UV in a separate tiled 816 * image from Y to reduce the column height, which is not supported 817 * with these modifiers. 818 */ 819 820 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 821 fourcc_mod_broadcom_code(2, v) 822 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 823 fourcc_mod_broadcom_code(3, v) 824 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 825 fourcc_mod_broadcom_code(4, v) 826 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 827 fourcc_mod_broadcom_code(5, v) 828 829 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 830 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 831 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 832 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 833 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 834 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 835 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 836 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 837 838 /* Broadcom UIF format 839 * 840 * This is the common format for the current Broadcom multimedia 841 * blocks, including V3D 3.x and newer, newer video codecs, and 842 * displays. 843 * 844 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 845 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 846 * stored in columns, with padding between the columns to ensure that 847 * moving from one column to the next doesn't hit the same SDRAM page 848 * bank. 849 * 850 * To calculate the padding, it is assumed that each hardware block 851 * and the software driving it knows the platform's SDRAM page size, 852 * number of banks, and XOR address, and that it's identical between 853 * all blocks using the format. This tiling modifier will use XOR as 854 * necessary to reduce the padding. If a hardware block can't do XOR, 855 * the assumption is that a no-XOR tiling modifier will be created. 856 */ 857 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 858 859 /* 860 * Arm Framebuffer Compression (AFBC) modifiers 861 * 862 * AFBC is a proprietary lossless image compression protocol and format. 863 * It provides fine-grained random access and minimizes the amount of data 864 * transferred between IP blocks. 865 * 866 * AFBC has several features which may be supported and/or used, which are 867 * represented using bits in the modifier. Not all combinations are valid, 868 * and different devices or use-cases may support different combinations. 869 * 870 * Further information on the use of AFBC modifiers can be found in 871 * Documentation/gpu/afbc.rst 872 */ 873 874 /* 875 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific 876 * modifiers) denote the category for modifiers. Currently we have only two 877 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen 878 * different categories. 879 */ 880 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ 881 fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) 882 883 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 884 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 885 886 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ 887 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) 888 889 /* 890 * AFBC superblock size 891 * 892 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 893 * size (in pixels) must be aligned to a multiple of the superblock size. 894 * Four lowest significant bits(LSBs) are reserved for block size. 895 * 896 * Where one superblock size is specified, it applies to all planes of the 897 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, 898 * the first applies to the Luma plane and the second applies to the Chroma 899 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). 900 * Multiple superblock sizes are only valid for multi-plane YCbCr formats. 901 */ 902 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 903 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 904 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 905 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) 906 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) 907 908 /* 909 * AFBC lossless colorspace transform 910 * 911 * Indicates that the buffer makes use of the AFBC lossless colorspace 912 * transform. 913 */ 914 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 915 916 /* 917 * AFBC block-split 918 * 919 * Indicates that the payload of each superblock is split. The second 920 * half of the payload is positioned at a predefined offset from the start 921 * of the superblock payload. 922 */ 923 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 924 925 /* 926 * AFBC sparse layout 927 * 928 * This flag indicates that the payload of each superblock must be stored at a 929 * predefined position relative to the other superblocks in the same AFBC 930 * buffer. This order is the same order used by the header buffer. In this mode 931 * each superblock is given the same amount of space as an uncompressed 932 * superblock of the particular format would require, rounding up to the next 933 * multiple of 128 bytes in size. 934 */ 935 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 936 937 /* 938 * AFBC copy-block restrict 939 * 940 * Buffers with this flag must obey the copy-block restriction. The restriction 941 * is such that there are no copy-blocks referring across the border of 8x8 942 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 943 */ 944 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 945 946 /* 947 * AFBC tiled layout 948 * 949 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 950 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 951 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 952 * larger bpp formats. The order between the tiles is scan line. 953 * When the tiled layout is used, the buffer size (in pixels) must be aligned 954 * to the tile size. 955 */ 956 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 957 958 /* 959 * AFBC solid color blocks 960 * 961 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 962 * can be reduced if a whole superblock is a single color. 963 */ 964 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 965 966 /* 967 * AFBC double-buffer 968 * 969 * Indicates that the buffer is allocated in a layout safe for front-buffer 970 * rendering. 971 */ 972 #define AFBC_FORMAT_MOD_DB (1ULL << 10) 973 974 /* 975 * AFBC buffer content hints 976 * 977 * Indicates that the buffer includes per-superblock content hints. 978 */ 979 #define AFBC_FORMAT_MOD_BCH (1ULL << 11) 980 981 /* AFBC uncompressed storage mode 982 * 983 * Indicates that the buffer is using AFBC uncompressed storage mode. 984 * In this mode all superblock payloads in the buffer use the uncompressed 985 * storage mode, which is usually only used for data which cannot be compressed. 986 * The buffer layout is the same as for AFBC buffers without USM set, this only 987 * affects the storage mode of the individual superblocks. Note that even a 988 * buffer without USM set may use uncompressed storage mode for some or all 989 * superblocks, USM just guarantees it for all. 990 */ 991 #define AFBC_FORMAT_MOD_USM (1ULL << 12) 992 993 /* 994 * Arm 16x16 Block U-Interleaved modifier 995 * 996 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image 997 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels 998 * in the block are reordered. 999 */ 1000 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ 1001 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) 1002 1003 /* 1004 * Allwinner tiled modifier 1005 * 1006 * This tiling mode is implemented by the VPU found on all Allwinner platforms, 1007 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 1008 * planes. 1009 * 1010 * With this tiling, the luminance samples are disposed in tiles representing 1011 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. 1012 * The pixel order in each tile is linear and the tiles are disposed linearly, 1013 * both in row-major order. 1014 */ 1015 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) 1016 1017 /* 1018 * Amlogic Video Framebuffer Compression modifiers 1019 * 1020 * Amlogic uses a proprietary lossless image compression protocol and format 1021 * for their hardware video codec accelerators, either video decoders or 1022 * video input encoders. 1023 * 1024 * It considerably reduces memory bandwidth while writing and reading 1025 * frames in memory. 1026 * 1027 * The underlying storage is considered to be 3 components, 8bit or 10-bit 1028 * per component YCbCr 420, single plane : 1029 * - DRM_FORMAT_YUV420_8BIT 1030 * - DRM_FORMAT_YUV420_10BIT 1031 * 1032 * The first 8 bits of the mode defines the layout, then the following 8 bits 1033 * defines the options changing the layout. 1034 * 1035 * Not all combinations are valid, and different SoCs may support different 1036 * combinations of layout and options. 1037 */ 1038 #define __fourcc_mod_amlogic_layout_mask 0xf 1039 #define __fourcc_mod_amlogic_options_shift 8 1040 #define __fourcc_mod_amlogic_options_mask 0xf 1041 1042 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ 1043 fourcc_mod_code(AMLOGIC, \ 1044 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ 1045 (((__options) & __fourcc_mod_amlogic_options_mask) \ 1046 << __fourcc_mod_amlogic_options_shift)) 1047 1048 /* Amlogic FBC Layouts */ 1049 1050 /* 1051 * Amlogic FBC Basic Layout 1052 * 1053 * The basic layout is composed of: 1054 * - a body content organized in 64x32 superblocks with 4096 bytes per 1055 * superblock in default mode. 1056 * - a 32 bytes per 128x64 header block 1057 * 1058 * This layout is transferrable between Amlogic SoCs supporting this modifier. 1059 */ 1060 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) 1061 1062 /* 1063 * Amlogic FBC Scatter Memory layout 1064 * 1065 * Indicates the header contains IOMMU references to the compressed 1066 * frames content to optimize memory access and layout. 1067 * 1068 * In this mode, only the header memory address is needed, thus the 1069 * content memory organization is tied to the current producer 1070 * execution and cannot be saved/dumped neither transferrable between 1071 * Amlogic SoCs supporting this modifier. 1072 * 1073 * Due to the nature of the layout, these buffers are not expected to 1074 * be accessible by the user-space clients, but only accessible by the 1075 * hardware producers and consumers. 1076 * 1077 * The user-space clients should expect a failure while trying to mmap 1078 * the DMA-BUF handle returned by the producer. 1079 */ 1080 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) 1081 1082 /* Amlogic FBC Layout Options Bit Mask */ 1083 1084 /* 1085 * Amlogic FBC Memory Saving mode 1086 * 1087 * Indicates the storage is packed when pixel size is multiple of word 1088 * boudaries, i.e. 8bit should be stored in this mode to save allocation 1089 * memory. 1090 * 1091 * This mode reduces body layout to 3072 bytes per 64x32 superblock with 1092 * the basic layout and 3200 bytes per 64x32 superblock combined with 1093 * the scatter layout. 1094 */ 1095 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) 1096 1097 /* 1098 * AMD modifiers 1099 * 1100 * Memory layout: 1101 * 1102 * without DCC: 1103 * - main surface 1104 * 1105 * with DCC & without DCC_RETILE: 1106 * - main surface in plane 0 1107 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) 1108 * 1109 * with DCC & DCC_RETILE: 1110 * - main surface in plane 0 1111 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) 1112 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) 1113 * 1114 * For multi-plane formats the above surfaces get merged into one plane for 1115 * each format plane, based on the required alignment only. 1116 * 1117 * Bits Parameter Notes 1118 * ----- ------------------------ --------------------------------------------- 1119 * 1120 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* 1121 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* 1122 * 13 DCC 1123 * 14 DCC_RETILE 1124 * 15 DCC_PIPE_ALIGN 1125 * 16 DCC_INDEPENDENT_64B 1126 * 17 DCC_INDEPENDENT_128B 1127 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* 1128 * 20 DCC_CONSTANT_ENCODE 1129 * 23:21 PIPE_XOR_BITS Only for some chips 1130 * 26:24 BANK_XOR_BITS Only for some chips 1131 * 29:27 PACKERS Only for some chips 1132 * 32:30 RB Only for some chips 1133 * 35:33 PIPE Only for some chips 1134 * 55:36 - Reserved for future use, must be zero 1135 */ 1136 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) 1137 1138 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) 1139 1140 /* Reserve 0 for GFX8 and older */ 1141 #define AMD_FMT_MOD_TILE_VER_GFX9 1 1142 #define AMD_FMT_MOD_TILE_VER_GFX10 2 1143 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 1144 1145 /* 1146 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical 1147 * version. 1148 */ 1149 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9 1150 1151 /* 1152 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has 1153 * GFX9 as canonical version. 1154 */ 1155 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 1156 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 1157 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 1158 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 1159 1160 #define AMD_FMT_MOD_DCC_BLOCK_64B 0 1161 #define AMD_FMT_MOD_DCC_BLOCK_128B 1 1162 #define AMD_FMT_MOD_DCC_BLOCK_256B 2 1163 1164 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 1165 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF 1166 #define AMD_FMT_MOD_TILE_SHIFT 8 1167 #define AMD_FMT_MOD_TILE_MASK 0x1F 1168 1169 /* Whether DCC compression is enabled. */ 1170 #define AMD_FMT_MOD_DCC_SHIFT 13 1171 #define AMD_FMT_MOD_DCC_MASK 0x1 1172 1173 /* 1174 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and 1175 * one which is not-aligned. 1176 */ 1177 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 1178 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 1179 1180 /* Only set if DCC_RETILE = false */ 1181 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 1182 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 1183 1184 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 1185 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 1186 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 1187 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 1188 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 1189 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 1190 1191 /* 1192 * DCC supports embedding some clear colors directly in the DCC surface. 1193 * However, on older GPUs the rendering HW ignores the embedded clear color 1194 * and prefers the driver provided color. This necessitates doing a fastclear 1195 * eliminate operation before a process transfers control. 1196 * 1197 * If this bit is set that means the fastclear eliminate is not needed for these 1198 * embeddable colors. 1199 */ 1200 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 1201 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 1202 1203 /* 1204 * The below fields are for accounting for per GPU differences. These are only 1205 * relevant for GFX9 and later and if the tile field is *_X/_T. 1206 * 1207 * PIPE_XOR_BITS = always needed 1208 * BANK_XOR_BITS = only for TILE_VER_GFX9 1209 * PACKERS = only for TILE_VER_GFX10_RBPLUS 1210 * RB = only for TILE_VER_GFX9 & DCC 1211 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) 1212 */ 1213 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 1214 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 1215 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 1216 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 1217 #define AMD_FMT_MOD_PACKERS_SHIFT 27 1218 #define AMD_FMT_MOD_PACKERS_MASK 0x7 1219 #define AMD_FMT_MOD_RB_SHIFT 30 1220 #define AMD_FMT_MOD_RB_MASK 0x7 1221 #define AMD_FMT_MOD_PIPE_SHIFT 33 1222 #define AMD_FMT_MOD_PIPE_MASK 0x7 1223 1224 #define AMD_FMT_MOD_SET(field, value) \ 1225 ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) 1226 #define AMD_FMT_MOD_GET(field, value) \ 1227 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) 1228 #define AMD_FMT_MOD_CLEAR(field) \ 1229 (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) 1230 1231 #if defined(__cplusplus) 1232 } 1233 #endif 1234 1235 #endif /* DRM_FOURCC_H */ 1236