1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 28 #if defined(__cplusplus) 29 extern "C" { 30 #endif 31 32 /** 33 * DOC: overview 34 * 35 * In the DRM subsystem, framebuffer pixel formats are described using the 36 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 37 * fourcc code, a Format Modifier may optionally be provided, in order to 38 * further describe the buffer's format - for example tiling or compression. 39 * 40 * Format Modifiers 41 * ---------------- 42 * 43 * Format modifiers are used in conjunction with a fourcc code, forming a 44 * unique fourcc:modifier pair. This format:modifier pair must fully define the 45 * format and data layout of the buffer, and should be the only way to describe 46 * that particular buffer. 47 * 48 * Having multiple fourcc:modifier pairs which describe the same layout should 49 * be avoided, as such aliases run the risk of different drivers exposing 50 * different names for the same data format, forcing userspace to understand 51 * that they are aliases. 52 * 53 * Format modifiers may change any property of the buffer, including the number 54 * of planes and/or the required allocation size. Format modifiers are 55 * vendor-namespaced, and as such the relationship between a fourcc code and a 56 * modifier is specific to the modifer being used. For example, some modifiers 57 * may preserve meaning - such as number of planes - from the fourcc code, 58 * whereas others may not. 59 * 60 * Modifiers must uniquely encode buffer layout. In other words, a buffer must 61 * match only a single modifier. A modifier must not be a subset of layouts of 62 * another modifier. For instance, it's incorrect to encode pitch alignment in 63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel 64 * aligned modifier. That said, modifiers can have implicit minimal 65 * requirements. 66 * 67 * For modifiers where the combination of fourcc code and modifier can alias, 68 * a canonical pair needs to be defined and used by all drivers. Preferred 69 * combinations are also encouraged where all combinations might lead to 70 * confusion and unnecessarily reduced interoperability. An example for the 71 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. 72 * 73 * There are two kinds of modifier users: 74 * 75 * - Kernel and user-space drivers: for drivers it's important that modifiers 76 * don't alias, otherwise two drivers might support the same format but use 77 * different aliases, preventing them from sharing buffers in an efficient 78 * format. 79 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users 80 * see modifiers as opaque tokens they can check for equality and intersect. 81 * These users musn't need to know to reason about the modifier value 82 * (i.e. they are not expected to extract information out of the modifier). 83 * 84 * Vendors should document their modifier usage in as much detail as 85 * possible, to ensure maximum compatibility across devices, drivers and 86 * applications. 87 * 88 * The authoritative list of format modifier codes is found in 89 * `include/uapi/drm/drm_fourcc.h` 90 * 91 * Open Source User Waiver 92 * ----------------------- 93 * 94 * Because this is the authoritative source for pixel formats and modifiers 95 * referenced by GL, Vulkan extensions and other standards and hence used both 96 * by open source and closed source driver stacks, the usual requirement for an 97 * upstream in-kernel or open source userspace user does not apply. 98 * 99 * To ensure, as much as feasible, compatibility across stacks and avoid 100 * confusion with incompatible enumerations stakeholders for all relevant driver 101 * stacks should approve additions. 102 */ 103 104 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ 105 ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) 106 107 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ 108 109 /* Reserve 0 for the invalid format specifier */ 110 #define DRM_FORMAT_INVALID 0 111 112 /* color index */ 113 #define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */ 114 #define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */ 115 #define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */ 116 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 117 118 /* 1 bpp Darkness (inverse relationship between channel value and brightness) */ 119 #define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */ 120 121 /* 2 bpp Darkness (inverse relationship between channel value and brightness) */ 122 #define DRM_FORMAT_D2 fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */ 123 124 /* 4 bpp Darkness (inverse relationship between channel value and brightness) */ 125 #define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */ 126 127 /* 8 bpp Darkness (inverse relationship between channel value and brightness) */ 128 #define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */ 129 130 /* 1 bpp Red (direct relationship between channel value and brightness) */ 131 #define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */ 132 133 /* 2 bpp Red (direct relationship between channel value and brightness) */ 134 #define DRM_FORMAT_R2 fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */ 135 136 /* 4 bpp Red (direct relationship between channel value and brightness) */ 137 #define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */ 138 139 /* 8 bpp Red (direct relationship between channel value and brightness) */ 140 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 141 142 /* 10 bpp Red (direct relationship between channel value and brightness) */ 143 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ 144 145 /* 12 bpp Red (direct relationship between channel value and brightness) */ 146 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ 147 148 /* 16 bpp Red (direct relationship between channel value and brightness) */ 149 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 150 151 /* 16 bpp RG */ 152 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 153 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 154 155 /* 32 bpp RG */ 156 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 157 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 158 159 /* 8 bpp RGB */ 160 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 161 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 162 163 /* 16 bpp RGB */ 164 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 165 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 166 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 167 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 168 169 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 170 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 171 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 172 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 173 174 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 175 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 176 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 177 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 178 179 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 180 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 181 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 182 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 183 184 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 185 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 186 187 /* 24 bpp RGB */ 188 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 189 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 190 191 /* 32 bpp RGB */ 192 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 193 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 194 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 195 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 196 197 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 198 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 199 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 200 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 201 202 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 203 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 204 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 205 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 206 207 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 208 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 209 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 210 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 211 212 /* 64 bpp RGB */ 213 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 214 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 215 216 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 217 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 218 219 /* 220 * Floating point 64bpp RGB 221 * IEEE 754-2008 binary16 half-precision float 222 * [15:0] sign:exponent:mantissa 1:5:10 223 */ 224 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 225 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 226 227 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 228 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 229 230 /* 231 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits 232 * of unused padding per component: 233 */ 234 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ 235 236 /* packed YCbCr */ 237 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 238 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 239 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 240 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 241 242 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 243 #define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */ 244 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 245 #define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */ 246 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ 247 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ 248 249 /* 250 * packed Y2xx indicate for each component, xx valid data occupy msb 251 * 16-xx padding occupy lsb 252 */ 253 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ 254 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ 255 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ 256 257 /* 258 * packed Y4xx indicate for each component, xx valid data occupy msb 259 * 16-xx padding occupy lsb except Y410 260 */ 261 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ 262 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 263 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ 264 265 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ 266 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 267 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ 268 269 /* 270 * packed YCbCr420 2x2 tiled formats 271 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 272 */ 273 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 274 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 275 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 276 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 277 278 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 279 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 280 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 281 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 282 283 /* 284 * 1-plane YUV 4:2:0 285 * In these formats, the component ordering is specified (Y, followed by U 286 * then V), but the exact Linear layout is undefined. 287 * These formats can only be used with a non-Linear modifier. 288 */ 289 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') 290 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') 291 292 /* 293 * 2 plane RGB + A 294 * index 0 = RGB plane, same format as the corresponding non _A8 format has 295 * index 1 = A plane, [7:0] A 296 */ 297 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 298 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 299 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 300 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 301 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 302 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 303 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 304 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 305 306 /* 307 * 2 plane YCbCr 308 * index 0 = Y plane, [7:0] Y 309 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 310 * or 311 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 312 */ 313 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 314 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 315 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 316 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 317 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 318 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 319 /* 320 * 2 plane YCbCr 321 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian 322 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian 323 */ 324 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ 325 326 /* 327 * 2 plane YCbCr MSB aligned 328 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 329 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 330 */ 331 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ 332 333 /* 334 * 2 plane YCbCr MSB aligned 335 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 336 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 337 */ 338 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ 339 340 /* 341 * 2 plane YCbCr MSB aligned 342 * index 0 = Y plane, [15:0] Y:x [12:4] little endian 343 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian 344 */ 345 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ 346 347 /* 348 * 2 plane YCbCr MSB aligned 349 * index 0 = Y plane, [15:0] Y little endian 350 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian 351 */ 352 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ 353 354 /* 2 plane YCbCr420. 355 * 3 10 bit components and 2 padding bits packed into 4 bytes. 356 * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian 357 * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian 358 */ 359 #define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */ 360 361 /* 3 plane non-subsampled (444) YCbCr 362 * 16 bits per component, but only 10 bits are used and 6 bits are padded 363 * index 0: Y plane, [15:0] Y:x [10:6] little endian 364 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian 365 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian 366 */ 367 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') 368 369 /* 3 plane non-subsampled (444) YCrCb 370 * 16 bits per component, but only 10 bits are used and 6 bits are padded 371 * index 0: Y plane, [15:0] Y:x [10:6] little endian 372 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian 373 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian 374 */ 375 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') 376 377 /* 378 * 3 plane YCbCr 379 * index 0: Y plane, [7:0] Y 380 * index 1: Cb plane, [7:0] Cb 381 * index 2: Cr plane, [7:0] Cr 382 * or 383 * index 1: Cr plane, [7:0] Cr 384 * index 2: Cb plane, [7:0] Cb 385 */ 386 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 387 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 388 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 389 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 390 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 391 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 392 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 393 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 394 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 395 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 396 397 398 /* 399 * Format Modifiers: 400 * 401 * Format modifiers describe, typically, a re-ordering or modification 402 * of the data in a plane of an FB. This can be used to express tiled/ 403 * swizzled formats, or compression, or a combination of the two. 404 * 405 * The upper 8 bits of the format modifier are a vendor-id as assigned 406 * below. The lower 56 bits are assigned as vendor sees fit. 407 */ 408 409 /* Vendor Ids: */ 410 #define DRM_FORMAT_MOD_VENDOR_NONE 0 411 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 412 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 413 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 414 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 415 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 416 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 417 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 418 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 419 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 420 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a 421 422 /* add more to the end as needed */ 423 424 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 425 426 #define fourcc_mod_get_vendor(modifier) \ 427 (((modifier) >> 56) & 0xff) 428 429 #define fourcc_mod_is_vendor(modifier, vendor) \ 430 (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) 431 432 #define fourcc_mod_code(vendor, val) \ 433 ((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 434 435 /* 436 * Format Modifier tokens: 437 * 438 * When adding a new token please document the layout with a code comment, 439 * similar to the fourcc codes above. drm_fourcc.h is considered the 440 * authoritative source for all of these. 441 * 442 * Generic modifier names: 443 * 444 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names 445 * for layouts which are common across multiple vendors. To preserve 446 * compatibility, in cases where a vendor-specific definition already exists and 447 * a generic name for it is desired, the common name is a purely symbolic alias 448 * and must use the same numerical value as the original definition. 449 * 450 * Note that generic names should only be used for modifiers which describe 451 * generic layouts (such as pixel re-ordering), which may have 452 * independently-developed support across multiple vendors. 453 * 454 * In future cases where a generic layout is identified before merging with a 455 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor 456 * 'NONE' could be considered. This should only be for obvious, exceptional 457 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only 458 * apply to a single vendor. 459 * 460 * Generic names should not be used for cases where multiple hardware vendors 461 * have implementations of the same standardised compression scheme (such as 462 * AFBC). In those cases, all implementations should use the same format 463 * modifier(s), reflecting the vendor of the standard. 464 */ 465 466 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE 467 468 /* 469 * Invalid Modifier 470 * 471 * This modifier can be used as a sentinel to terminate the format modifiers 472 * list, or to initialize a variable with an invalid modifier. It might also be 473 * used to report an error back to userspace for certain APIs. 474 */ 475 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 476 477 /* 478 * Linear Layout 479 * 480 * Just plain linear layout. Note that this is different from no specifying any 481 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 482 * which tells the driver to also take driver-internal information into account 483 * and so might actually result in a tiled framebuffer. 484 */ 485 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 486 487 /* 488 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead 489 * 490 * The "none" format modifier doesn't actually mean that the modifier is 491 * implicit, instead it means that the layout is linear. Whether modifiers are 492 * used is out-of-band information carried in an API-specific way (e.g. in a 493 * flag for drm_mode_fb_cmd2). 494 */ 495 #define DRM_FORMAT_MOD_NONE 0 496 497 /* Intel framebuffer modifiers */ 498 499 /* 500 * Intel X-tiling layout 501 * 502 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 503 * in row-major layout. Within the tile bytes are laid out row-major, with 504 * a platform-dependent stride. On top of that the memory can apply 505 * platform-depending swizzling of some higher address bits into bit6. 506 * 507 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 508 * On earlier platforms the is highly platforms specific and not useful for 509 * cross-driver sharing. It exists since on a given platform it does uniquely 510 * identify the layout in a simple way for i915-specific userspace, which 511 * facilitated conversion of userspace to modifiers. Additionally the exact 512 * format on some really old platforms is not known. 513 */ 514 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 515 516 /* 517 * Intel Y-tiling layout 518 * 519 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 520 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 521 * chunks column-major, with a platform-dependent height. On top of that the 522 * memory can apply platform-depending swizzling of some higher address bits 523 * into bit6. 524 * 525 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 526 * On earlier platforms the is highly platforms specific and not useful for 527 * cross-driver sharing. It exists since on a given platform it does uniquely 528 * identify the layout in a simple way for i915-specific userspace, which 529 * facilitated conversion of userspace to modifiers. Additionally the exact 530 * format on some really old platforms is not known. 531 */ 532 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 533 534 /* 535 * Intel Yf-tiling layout 536 * 537 * This is a tiled layout using 4Kb tiles in row-major layout. 538 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 539 * are arranged in four groups (two wide, two high) with column-major layout. 540 * Each group therefore consits out of four 256 byte units, which are also laid 541 * out as 2x2 column-major. 542 * 256 byte units are made out of four 64 byte blocks of pixels, producing 543 * either a square block or a 2:1 unit. 544 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 545 * in pixel depends on the pixel depth. 546 */ 547 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 548 549 /* 550 * Intel color control surface (CCS) for render compression 551 * 552 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 553 * The main surface will be plane index 0 and must be Y/Yf-tiled, 554 * the CCS will be plane index 1. 555 * 556 * Each CCS tile matches a 1024x512 pixel area of the main surface. 557 * To match certain aspects of the 3D hardware the CCS is 558 * considered to be made up of normal 128Bx32 Y tiles, Thus 559 * the CCS pitch must be specified in multiples of 128 bytes. 560 * 561 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 562 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 563 * But that fact is not relevant unless the memory is accessed 564 * directly. 565 */ 566 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 567 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 568 569 /* 570 * Intel color control surfaces (CCS) for Gen-12 render compression. 571 * 572 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 573 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 574 * main surface. In other words, 4 bits in CCS map to a main surface cache 575 * line pair. The main surface pitch is required to be a multiple of four 576 * Y-tile widths. 577 */ 578 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) 579 580 /* 581 * Intel color control surfaces (CCS) for Gen-12 media compression 582 * 583 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 584 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 585 * main surface. In other words, 4 bits in CCS map to a main surface cache 586 * line pair. The main surface pitch is required to be a multiple of four 587 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the 588 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 589 * planes 2 and 3 for the respective CCS. 590 */ 591 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) 592 593 /* 594 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render 595 * compression. 596 * 597 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear 598 * and at index 1. The clear color is stored at index 2, and the pitch should 599 * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits 600 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 601 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 602 * the converted clear color of size 64 bits. The first 32 bits store the Lower 603 * Converted Clear Color value and the next 32 bits store the Higher Converted 604 * Clear Color value when applicable. The Converted Clear Color values are 605 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 606 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 607 * corresponds to an area of 4x1 tiles in the main surface. The main surface 608 * pitch is required to be a multiple of 4 tile widths. 609 */ 610 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) 611 612 /* 613 * Intel Tile 4 layout 614 * 615 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same 616 * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It 617 * only differs from Tile Y at the 256B granularity in between. At this 618 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape 619 * of 64B x 8 rows. 620 */ 621 #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) 622 623 /* 624 * Intel color control surfaces (CCS) for DG2 render compression. 625 * 626 * The main surface is Tile 4 and at plane index 0. The CCS data is stored 627 * outside of the GEM object in a reserved memory area dedicated for the 628 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The 629 * main surface pitch is required to be a multiple of four Tile 4 widths. 630 */ 631 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10) 632 633 /* 634 * Intel color control surfaces (CCS) for DG2 media compression. 635 * 636 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 637 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 638 * 0 and 1, respectively. The CCS for all planes are stored outside of the 639 * GEM object in a reserved memory area dedicated for the storage of the 640 * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface 641 * pitch is required to be a multiple of four Tile 4 widths. 642 */ 643 #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11) 644 645 /* 646 * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression. 647 * 648 * The main surface is Tile 4 and at plane index 0. The CCS data is stored 649 * outside of the GEM object in a reserved memory area dedicated for the 650 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The 651 * main surface pitch is required to be a multiple of four Tile 4 widths. The 652 * clear color is stored at plane index 1 and the pitch should be 64 bytes 653 * aligned. The format of the 256 bits of clear color data matches the one used 654 * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description 655 * for details. 656 */ 657 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) 658 659 /* 660 * Intel Color Control Surfaces (CCS) for display ver. 14 render compression. 661 * 662 * The main surface is tile4 and at plane index 0, the CCS is linear and 663 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 664 * main surface. In other words, 4 bits in CCS map to a main surface cache 665 * line pair. The main surface pitch is required to be a multiple of four 666 * tile4 widths. 667 */ 668 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13) 669 670 /* 671 * Intel Color Control Surfaces (CCS) for display ver. 14 media compression 672 * 673 * The main surface is tile4 and at plane index 0, the CCS is linear and 674 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 675 * main surface. In other words, 4 bits in CCS map to a main surface cache 676 * line pair. The main surface pitch is required to be a multiple of four 677 * tile4 widths. For semi-planar formats like NV12, CCS planes follow the 678 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 679 * planes 2 and 3 for the respective CCS. 680 */ 681 #define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14) 682 683 /* 684 * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render 685 * compression. 686 * 687 * The main surface is tile4 and is at plane index 0 whereas CCS is linear 688 * and at index 1. The clear color is stored at index 2, and the pitch should 689 * be ignored. The clear color structure is 256 bits. The first 128 bits 690 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 691 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 692 * the converted clear color of size 64 bits. The first 32 bits store the Lower 693 * Converted Clear Color value and the next 32 bits store the Higher Converted 694 * Clear Color value when applicable. The Converted Clear Color values are 695 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 696 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 697 * corresponds to an area of 4x1 tiles in the main surface. The main surface 698 * pitch is required to be a multiple of 4 tile widths. 699 */ 700 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) 701 702 /* 703 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 704 * 705 * Macroblocks are laid in a Z-shape, and each pixel data is following the 706 * standard NV12 style. 707 * As for NV12, an image is the result of two frame buffers: one for Y, 708 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 709 * Alignment requirements are (for each buffer): 710 * - multiple of 128 pixels for the width 711 * - multiple of 32 pixels for the height 712 * 713 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 714 */ 715 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 716 717 /* 718 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 719 * 720 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 721 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 722 * they correspond to their 16x16 luma block. 723 */ 724 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 725 726 /* 727 * Qualcomm Compressed Format 728 * 729 * Refers to a compressed variant of the base format that is compressed. 730 * Implementation may be platform and base-format specific. 731 * 732 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 733 * Pixel data pitch/stride is aligned with macrotile width. 734 * Pixel data height is aligned with macrotile height. 735 * Entire pixel data buffer is aligned with 4k(bytes). 736 */ 737 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 738 739 /* 740 * Qualcomm Tiled Format 741 * 742 * Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed. 743 * Implementation may be platform and base-format specific. 744 * 745 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 746 * Pixel data pitch/stride is aligned with macrotile width. 747 * Pixel data height is aligned with macrotile height. 748 * Entire pixel data buffer is aligned with 4k(bytes). 749 */ 750 #define DRM_FORMAT_MOD_QCOM_TILED3 fourcc_mod_code(QCOM, 3) 751 752 /* 753 * Qualcomm Alternate Tiled Format 754 * 755 * Alternate tiled format typically only used within GMEM. 756 * Implementation may be platform and base-format specific. 757 */ 758 #define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2) 759 760 761 /* Vivante framebuffer modifiers */ 762 763 /* 764 * Vivante 4x4 tiling layout 765 * 766 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 767 * layout. 768 */ 769 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 770 771 /* 772 * Vivante 64x64 super-tiling layout 773 * 774 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 775 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 776 * major layout. 777 * 778 * For more information: see 779 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 780 */ 781 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 782 783 /* 784 * Vivante 4x4 tiling layout for dual-pipe 785 * 786 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 787 * different base address. Offsets from the base addresses are therefore halved 788 * compared to the non-split tiled layout. 789 */ 790 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 791 792 /* 793 * Vivante 64x64 super-tiling layout for dual-pipe 794 * 795 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 796 * starts at a different base address. Offsets from the base addresses are 797 * therefore halved compared to the non-split super-tiled layout. 798 */ 799 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 800 801 /* 802 * Vivante TS (tile-status) buffer modifiers. They can be combined with all of 803 * the color buffer tiling modifiers defined above. When TS is present it's a 804 * separate buffer containing the clear/compression status of each tile. The 805 * modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color buffer 806 * tile size in bytes covered by one entry in the status buffer and s is the 807 * number of status bits per entry. 808 * We reserve the top 8 bits of the Vivante modifier space for tile status 809 * clear/compression modifiers, as future cores might add some more TS layout 810 * variations. 811 */ 812 #define VIVANTE_MOD_TS_64_4 (1ULL << 48) 813 #define VIVANTE_MOD_TS_64_2 (2ULL << 48) 814 #define VIVANTE_MOD_TS_128_4 (3ULL << 48) 815 #define VIVANTE_MOD_TS_256_4 (4ULL << 48) 816 #define VIVANTE_MOD_TS_MASK (0xfULL << 48) 817 818 /* 819 * Vivante compression modifiers. Those depend on a TS modifier being present 820 * as the TS bits get reinterpreted as compression tags instead of simple 821 * clear markers when compression is enabled. 822 */ 823 #define VIVANTE_MOD_COMP_DEC400 (1ULL << 52) 824 #define VIVANTE_MOD_COMP_MASK (0xfULL << 52) 825 826 /* Masking out the extension bits will yield the base modifier. */ 827 #define VIVANTE_MOD_EXT_MASK (VIVANTE_MOD_TS_MASK | \ 828 VIVANTE_MOD_COMP_MASK) 829 830 /* NVIDIA frame buffer modifiers */ 831 832 /* 833 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 834 * 835 * Pixels are arranged in simple tiles of 16 x 16 bytes. 836 */ 837 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 838 839 /* 840 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, 841 * and Tegra GPUs starting with Tegra K1. 842 * 843 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies 844 * based on the architecture generation. GOBs themselves are then arranged in 845 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power 846 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents 847 * a block depth or height of "4"). 848 * 849 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 850 * in full detail. 851 * 852 * Macro 853 * Bits Param Description 854 * ---- ----- ----------------------------------------------------------------- 855 * 856 * 3:0 h log2(height) of each block, in GOBs. Placed here for 857 * compatibility with the existing 858 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 859 * 860 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for 861 * compatibility with the existing 862 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 863 * 864 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block 865 * size). Must be zero. 866 * 867 * Note there is no log2(width) parameter. Some portions of the 868 * hardware support a block width of two gobs, but it is impractical 869 * to use due to lack of support elsewhere, and has no known 870 * benefits. 871 * 872 * 11:9 - Reserved (To support 2D-array textures with variable array stride 873 * in blocks, specified via log2(tile width in blocks)). Must be 874 * zero. 875 * 876 * 19:12 k Page Kind. This value directly maps to a field in the page 877 * tables of all GPUs >= NV50. It affects the exact layout of bits 878 * in memory and can be derived from the tuple 879 * 880 * (format, GPU model, compression type, samples per pixel) 881 * 882 * Where compression type is defined below. If GPU model were 883 * implied by the format modifier, format, or memory buffer, page 884 * kind would not need to be included in the modifier itself, but 885 * since the modifier should define the layout of the associated 886 * memory buffer independent from any device or other context, it 887 * must be included here. 888 * 889 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed 890 * starting with Fermi GPUs. Additionally, the mapping between page 891 * kind and bit layout has changed at various points. 892 * 893 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping 894 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping 895 * 2 = Gob Height 8, Turing+ Page Kind mapping 896 * 3 = Reserved for future use. 897 * 898 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 899 * bit remapping step that occurs at an even lower level than the 900 * page kind and block linear swizzles. This causes the layout of 901 * surfaces mapped in those SOC's GPUs to be incompatible with the 902 * equivalent mapping on other GPUs in the same system. 903 * 904 * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 905 * 1 = Desktop GPU and Tegra Xavier+ Layout 906 * 907 * 25:23 c Lossless Framebuffer Compression type. 908 * 909 * 0 = none 910 * 1 = ROP/3D, layout 1, exact compression format implied by Page 911 * Kind field 912 * 2 = ROP/3D, layout 2, exact compression format implied by Page 913 * Kind field 914 * 3 = CDE horizontal 915 * 4 = CDE vertical 916 * 5 = Reserved for future use 917 * 6 = Reserved for future use 918 * 7 = Reserved for future use 919 * 920 * 55:25 - Reserved for future use. Must be zero. 921 */ 922 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 923 fourcc_mod_code(NVIDIA, (0x10 | \ 924 ((h) & 0xf) | \ 925 (((k) & 0xff) << 12) | \ 926 (((g) & 0x3) << 20) | \ 927 (((s) & 0x1) << 22) | \ 928 (((c) & 0x7) << 23))) 929 930 /* To grandfather in prior block linear format modifiers to the above layout, 931 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable 932 * with block-linear layouts, is remapped within drivers to the value 0xfe, 933 * which corresponds to the "generic" kind used for simple single-sample 934 * uncompressed color formats on Fermi - Volta GPUs. 935 */ 936 static inline uint64_t 937 drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier) 938 { 939 if (!(modifier & 0x10) || (modifier & (0xff << 12))) 940 return modifier; 941 else 942 return modifier | (0xfe << 12); 943 } 944 945 /* 946 * 16Bx2 Block Linear layout, used by Tegra K1 and later 947 * 948 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 949 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 950 * 951 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 952 * 953 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 954 * Valid values are: 955 * 956 * 0 == ONE_GOB 957 * 1 == TWO_GOBS 958 * 2 == FOUR_GOBS 959 * 3 == EIGHT_GOBS 960 * 4 == SIXTEEN_GOBS 961 * 5 == THIRTYTWO_GOBS 962 * 963 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 964 * in full detail. 965 */ 966 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 967 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) 968 969 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 970 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) 971 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 972 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) 973 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 974 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) 975 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 976 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) 977 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 978 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) 979 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 980 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) 981 982 /* 983 * Some Broadcom modifiers take parameters, for example the number of 984 * vertical lines in the image. Reserve the lower 32 bits for modifier 985 * type, and the next 24 bits for parameters. Top 8 bits are the 986 * vendor code. 987 */ 988 #define __fourcc_mod_broadcom_param_shift 8 989 #define __fourcc_mod_broadcom_param_bits 48 990 #define fourcc_mod_broadcom_code(val, params) \ 991 fourcc_mod_code(BROADCOM, ((((uint64_t)params) << __fourcc_mod_broadcom_param_shift) | val)) 992 #define fourcc_mod_broadcom_param(m) \ 993 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 994 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 995 #define fourcc_mod_broadcom_mod(m) \ 996 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 997 __fourcc_mod_broadcom_param_shift)) 998 999 /* 1000 * Broadcom VC4 "T" format 1001 * 1002 * This is the primary layout that the V3D GPU can texture from (it 1003 * can't do linear). The T format has: 1004 * 1005 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 1006 * pixels at 32 bit depth. 1007 * 1008 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 1009 * 16x16 pixels). 1010 * 1011 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 1012 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 1013 * they're (TR, BR, BL, TL), where bottom left is start of memory. 1014 * 1015 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 1016 * tiles) or right-to-left (odd rows of 4k tiles). 1017 */ 1018 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 1019 1020 /* 1021 * Broadcom SAND format 1022 * 1023 * This is the native format that the H.264 codec block uses. For VC4 1024 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 1025 * 1026 * The image can be considered to be split into columns, and the 1027 * columns are placed consecutively into memory. The width of those 1028 * columns can be either 32, 64, 128, or 256 pixels, but in practice 1029 * only 128 pixel columns are used. 1030 * 1031 * The pitch between the start of each column is set to optimally 1032 * switch between SDRAM banks. This is passed as the number of lines 1033 * of column width in the modifier (we can't use the stride value due 1034 * to various core checks that look at it , so you should set the 1035 * stride to width*cpp). 1036 * 1037 * Note that the column height for this format modifier is the same 1038 * for all of the planes, assuming that each column contains both Y 1039 * and UV. Some SAND-using hardware stores UV in a separate tiled 1040 * image from Y to reduce the column height, which is not supported 1041 * with these modifiers. 1042 * 1043 * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also 1044 * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes 1045 * wide, but as this is a 10 bpp format that translates to 96 pixels. 1046 */ 1047 1048 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 1049 fourcc_mod_broadcom_code(2, v) 1050 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 1051 fourcc_mod_broadcom_code(3, v) 1052 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 1053 fourcc_mod_broadcom_code(4, v) 1054 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 1055 fourcc_mod_broadcom_code(5, v) 1056 1057 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 1058 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 1059 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 1060 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 1061 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 1062 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 1063 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 1064 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 1065 1066 /* Broadcom UIF format 1067 * 1068 * This is the common format for the current Broadcom multimedia 1069 * blocks, including V3D 3.x and newer, newer video codecs, and 1070 * displays. 1071 * 1072 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 1073 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 1074 * stored in columns, with padding between the columns to ensure that 1075 * moving from one column to the next doesn't hit the same SDRAM page 1076 * bank. 1077 * 1078 * To calculate the padding, it is assumed that each hardware block 1079 * and the software driving it knows the platform's SDRAM page size, 1080 * number of banks, and XOR address, and that it's identical between 1081 * all blocks using the format. This tiling modifier will use XOR as 1082 * necessary to reduce the padding. If a hardware block can't do XOR, 1083 * the assumption is that a no-XOR tiling modifier will be created. 1084 */ 1085 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 1086 1087 /* 1088 * Arm Framebuffer Compression (AFBC) modifiers 1089 * 1090 * AFBC is a proprietary lossless image compression protocol and format. 1091 * It provides fine-grained random access and minimizes the amount of data 1092 * transferred between IP blocks. 1093 * 1094 * AFBC has several features which may be supported and/or used, which are 1095 * represented using bits in the modifier. Not all combinations are valid, 1096 * and different devices or use-cases may support different combinations. 1097 * 1098 * Further information on the use of AFBC modifiers can be found in 1099 * Documentation/gpu/afbc.rst 1100 */ 1101 1102 /* 1103 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific 1104 * modifiers) denote the category for modifiers. Currently we have three 1105 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of 1106 * sixteen different categories. 1107 */ 1108 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ 1109 fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) 1110 1111 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 1112 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 1113 1114 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ 1115 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) 1116 1117 /* 1118 * AFBC superblock size 1119 * 1120 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 1121 * size (in pixels) must be aligned to a multiple of the superblock size. 1122 * Four lowest significant bits(LSBs) are reserved for block size. 1123 * 1124 * Where one superblock size is specified, it applies to all planes of the 1125 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, 1126 * the first applies to the Luma plane and the second applies to the Chroma 1127 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). 1128 * Multiple superblock sizes are only valid for multi-plane YCbCr formats. 1129 */ 1130 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 1131 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 1132 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 1133 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) 1134 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) 1135 1136 /* 1137 * AFBC lossless colorspace transform 1138 * 1139 * Indicates that the buffer makes use of the AFBC lossless colorspace 1140 * transform. 1141 */ 1142 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 1143 1144 /* 1145 * AFBC block-split 1146 * 1147 * Indicates that the payload of each superblock is split. The second 1148 * half of the payload is positioned at a predefined offset from the start 1149 * of the superblock payload. 1150 */ 1151 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 1152 1153 /* 1154 * AFBC sparse layout 1155 * 1156 * This flag indicates that the payload of each superblock must be stored at a 1157 * predefined position relative to the other superblocks in the same AFBC 1158 * buffer. This order is the same order used by the header buffer. In this mode 1159 * each superblock is given the same amount of space as an uncompressed 1160 * superblock of the particular format would require, rounding up to the next 1161 * multiple of 128 bytes in size. 1162 */ 1163 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 1164 1165 /* 1166 * AFBC copy-block restrict 1167 * 1168 * Buffers with this flag must obey the copy-block restriction. The restriction 1169 * is such that there are no copy-blocks referring across the border of 8x8 1170 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 1171 */ 1172 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 1173 1174 /* 1175 * AFBC tiled layout 1176 * 1177 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 1178 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 1179 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 1180 * larger bpp formats. The order between the tiles is scan line. 1181 * When the tiled layout is used, the buffer size (in pixels) must be aligned 1182 * to the tile size. 1183 */ 1184 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 1185 1186 /* 1187 * AFBC solid color blocks 1188 * 1189 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 1190 * can be reduced if a whole superblock is a single color. 1191 */ 1192 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 1193 1194 /* 1195 * AFBC double-buffer 1196 * 1197 * Indicates that the buffer is allocated in a layout safe for front-buffer 1198 * rendering. 1199 */ 1200 #define AFBC_FORMAT_MOD_DB (1ULL << 10) 1201 1202 /* 1203 * AFBC buffer content hints 1204 * 1205 * Indicates that the buffer includes per-superblock content hints. 1206 */ 1207 #define AFBC_FORMAT_MOD_BCH (1ULL << 11) 1208 1209 /* AFBC uncompressed storage mode 1210 * 1211 * Indicates that the buffer is using AFBC uncompressed storage mode. 1212 * In this mode all superblock payloads in the buffer use the uncompressed 1213 * storage mode, which is usually only used for data which cannot be compressed. 1214 * The buffer layout is the same as for AFBC buffers without USM set, this only 1215 * affects the storage mode of the individual superblocks. Note that even a 1216 * buffer without USM set may use uncompressed storage mode for some or all 1217 * superblocks, USM just guarantees it for all. 1218 */ 1219 #define AFBC_FORMAT_MOD_USM (1ULL << 12) 1220 1221 /* 1222 * Arm Fixed-Rate Compression (AFRC) modifiers 1223 * 1224 * AFRC is a proprietary fixed rate image compression protocol and format, 1225 * designed to provide guaranteed bandwidth and memory footprint 1226 * reductions in graphics and media use-cases. 1227 * 1228 * AFRC buffers consist of one or more planes, with the same components 1229 * and meaning as an uncompressed buffer using the same pixel format. 1230 * 1231 * Within each plane, the pixel/luma/chroma values are grouped into 1232 * "coding unit" blocks which are individually compressed to a 1233 * fixed size (in bytes). All coding units within a given plane of a buffer 1234 * store the same number of values, and have the same compressed size. 1235 * 1236 * The coding unit size is configurable, allowing different rates of compression. 1237 * 1238 * The start of each AFRC buffer plane must be aligned to an alignment granule which 1239 * depends on the coding unit size. 1240 * 1241 * Coding Unit Size Plane Alignment 1242 * ---------------- --------------- 1243 * 16 bytes 1024 bytes 1244 * 24 bytes 512 bytes 1245 * 32 bytes 2048 bytes 1246 * 1247 * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned 1248 * to a multiple of the paging tile dimensions. 1249 * The dimensions of each paging tile depend on whether the buffer is optimised for 1250 * scanline (SCAN layout) or rotated (ROT layout) access. 1251 * 1252 * Layout Paging Tile Width Paging Tile Height 1253 * ------ ----------------- ------------------ 1254 * SCAN 16 coding units 4 coding units 1255 * ROT 8 coding units 8 coding units 1256 * 1257 * The dimensions of each coding unit depend on the number of components 1258 * in the compressed plane and whether the buffer is optimised for 1259 * scanline (SCAN layout) or rotated (ROT layout) access. 1260 * 1261 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height 1262 * ----------------------------- --------- ----------------- ------------------ 1263 * 1 SCAN 16 samples 4 samples 1264 * Example: 16x4 luma samples in a 'Y' plane 1265 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1266 * ----------------------------- --------- ----------------- ------------------ 1267 * 1 ROT 8 samples 8 samples 1268 * Example: 8x8 luma samples in a 'Y' plane 1269 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1270 * ----------------------------- --------- ----------------- ------------------ 1271 * 2 DONT CARE 8 samples 4 samples 1272 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer 1273 * ----------------------------- --------- ----------------- ------------------ 1274 * 3 DONT CARE 4 samples 4 samples 1275 * Example: 4x4 pixels in an RGB buffer without alpha 1276 * ----------------------------- --------- ----------------- ------------------ 1277 * 4 DONT CARE 4 samples 4 samples 1278 * Example: 4x4 pixels in an RGB buffer with alpha 1279 */ 1280 1281 #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 1282 1283 #define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ 1284 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) 1285 1286 /* 1287 * AFRC coding unit size modifier. 1288 * 1289 * Indicates the number of bytes used to store each compressed coding unit for 1290 * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance 1291 * is the same for both Cb and Cr, which may be stored in separate planes. 1292 * 1293 * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store 1294 * each compressed coding unit in the first plane of the buffer. For RGBA buffers 1295 * this is the only plane, while for semi-planar and fully-planar YUV buffers, 1296 * this corresponds to the luma plane. 1297 * 1298 * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store 1299 * each compressed coding unit in the second and third planes in the buffer. 1300 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s). 1301 * 1302 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified 1303 * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero. 1304 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and 1305 * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified. 1306 */ 1307 #define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf 1308 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL) 1309 #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL) 1310 #define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL) 1311 1312 #define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size) 1313 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4) 1314 1315 /* 1316 * AFRC scanline memory layout. 1317 * 1318 * Indicates if the buffer uses the scanline-optimised layout 1319 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout. 1320 * The memory layout is the same for all planes. 1321 */ 1322 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) 1323 1324 /* 1325 * Arm 16x16 Block U-Interleaved modifier 1326 * 1327 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image 1328 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels 1329 * in the block are reordered. 1330 */ 1331 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ 1332 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) 1333 1334 /* 1335 * Allwinner tiled modifier 1336 * 1337 * This tiling mode is implemented by the VPU found on all Allwinner platforms, 1338 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 1339 * planes. 1340 * 1341 * With this tiling, the luminance samples are disposed in tiles representing 1342 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. 1343 * The pixel order in each tile is linear and the tiles are disposed linearly, 1344 * both in row-major order. 1345 */ 1346 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) 1347 1348 /* 1349 * Amlogic Video Framebuffer Compression modifiers 1350 * 1351 * Amlogic uses a proprietary lossless image compression protocol and format 1352 * for their hardware video codec accelerators, either video decoders or 1353 * video input encoders. 1354 * 1355 * It considerably reduces memory bandwidth while writing and reading 1356 * frames in memory. 1357 * 1358 * The underlying storage is considered to be 3 components, 8bit or 10-bit 1359 * per component YCbCr 420, single plane : 1360 * - DRM_FORMAT_YUV420_8BIT 1361 * - DRM_FORMAT_YUV420_10BIT 1362 * 1363 * The first 8 bits of the mode defines the layout, then the following 8 bits 1364 * defines the options changing the layout. 1365 * 1366 * Not all combinations are valid, and different SoCs may support different 1367 * combinations of layout and options. 1368 */ 1369 #define __fourcc_mod_amlogic_layout_mask 0xff 1370 #define __fourcc_mod_amlogic_options_shift 8 1371 #define __fourcc_mod_amlogic_options_mask 0xff 1372 1373 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ 1374 fourcc_mod_code(AMLOGIC, \ 1375 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ 1376 (((__options) & __fourcc_mod_amlogic_options_mask) \ 1377 << __fourcc_mod_amlogic_options_shift)) 1378 1379 /* Amlogic FBC Layouts */ 1380 1381 /* 1382 * Amlogic FBC Basic Layout 1383 * 1384 * The basic layout is composed of: 1385 * - a body content organized in 64x32 superblocks with 4096 bytes per 1386 * superblock in default mode. 1387 * - a 32 bytes per 128x64 header block 1388 * 1389 * This layout is transferrable between Amlogic SoCs supporting this modifier. 1390 */ 1391 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) 1392 1393 /* 1394 * Amlogic FBC Scatter Memory layout 1395 * 1396 * Indicates the header contains IOMMU references to the compressed 1397 * frames content to optimize memory access and layout. 1398 * 1399 * In this mode, only the header memory address is needed, thus the 1400 * content memory organization is tied to the current producer 1401 * execution and cannot be saved/dumped neither transferrable between 1402 * Amlogic SoCs supporting this modifier. 1403 * 1404 * Due to the nature of the layout, these buffers are not expected to 1405 * be accessible by the user-space clients, but only accessible by the 1406 * hardware producers and consumers. 1407 * 1408 * The user-space clients should expect a failure while trying to mmap 1409 * the DMA-BUF handle returned by the producer. 1410 */ 1411 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) 1412 1413 /* Amlogic FBC Layout Options Bit Mask */ 1414 1415 /* 1416 * Amlogic FBC Memory Saving mode 1417 * 1418 * Indicates the storage is packed when pixel size is multiple of word 1419 * boudaries, i.e. 8bit should be stored in this mode to save allocation 1420 * memory. 1421 * 1422 * This mode reduces body layout to 3072 bytes per 64x32 superblock with 1423 * the basic layout and 3200 bytes per 64x32 superblock combined with 1424 * the scatter layout. 1425 */ 1426 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) 1427 1428 /* 1429 * AMD modifiers 1430 * 1431 * Memory layout: 1432 * 1433 * without DCC: 1434 * - main surface 1435 * 1436 * with DCC & without DCC_RETILE: 1437 * - main surface in plane 0 1438 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) 1439 * 1440 * with DCC & DCC_RETILE: 1441 * - main surface in plane 0 1442 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) 1443 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) 1444 * 1445 * For multi-plane formats the above surfaces get merged into one plane for 1446 * each format plane, based on the required alignment only. 1447 * 1448 * Bits Parameter Notes 1449 * ----- ------------------------ --------------------------------------------- 1450 * 1451 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* 1452 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* 1453 * 13 DCC 1454 * 14 DCC_RETILE 1455 * 15 DCC_PIPE_ALIGN 1456 * 16 DCC_INDEPENDENT_64B 1457 * 17 DCC_INDEPENDENT_128B 1458 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* 1459 * 20 DCC_CONSTANT_ENCODE 1460 * 23:21 PIPE_XOR_BITS Only for some chips 1461 * 26:24 BANK_XOR_BITS Only for some chips 1462 * 29:27 PACKERS Only for some chips 1463 * 32:30 RB Only for some chips 1464 * 35:33 PIPE Only for some chips 1465 * 55:36 - Reserved for future use, must be zero 1466 */ 1467 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) 1468 1469 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) 1470 1471 /* Reserve 0 for GFX8 and older */ 1472 #define AMD_FMT_MOD_TILE_VER_GFX9 1 1473 #define AMD_FMT_MOD_TILE_VER_GFX10 2 1474 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 1475 #define AMD_FMT_MOD_TILE_VER_GFX11 4 1476 1477 /* 1478 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical 1479 * version. 1480 */ 1481 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9 1482 1483 /* 1484 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has 1485 * GFX9 as canonical version. 1486 */ 1487 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 1488 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 1489 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 1490 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 1491 #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 1492 1493 #define AMD_FMT_MOD_DCC_BLOCK_64B 0 1494 #define AMD_FMT_MOD_DCC_BLOCK_128B 1 1495 #define AMD_FMT_MOD_DCC_BLOCK_256B 2 1496 1497 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 1498 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF 1499 #define AMD_FMT_MOD_TILE_SHIFT 8 1500 #define AMD_FMT_MOD_TILE_MASK 0x1F 1501 1502 /* Whether DCC compression is enabled. */ 1503 #define AMD_FMT_MOD_DCC_SHIFT 13 1504 #define AMD_FMT_MOD_DCC_MASK 0x1 1505 1506 /* 1507 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and 1508 * one which is not-aligned. 1509 */ 1510 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 1511 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 1512 1513 /* Only set if DCC_RETILE = false */ 1514 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 1515 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 1516 1517 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 1518 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 1519 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 1520 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 1521 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 1522 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 1523 1524 /* 1525 * DCC supports embedding some clear colors directly in the DCC surface. 1526 * However, on older GPUs the rendering HW ignores the embedded clear color 1527 * and prefers the driver provided color. This necessitates doing a fastclear 1528 * eliminate operation before a process transfers control. 1529 * 1530 * If this bit is set that means the fastclear eliminate is not needed for these 1531 * embeddable colors. 1532 */ 1533 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 1534 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 1535 1536 /* 1537 * The below fields are for accounting for per GPU differences. These are only 1538 * relevant for GFX9 and later and if the tile field is *_X/_T. 1539 * 1540 * PIPE_XOR_BITS = always needed 1541 * BANK_XOR_BITS = only for TILE_VER_GFX9 1542 * PACKERS = only for TILE_VER_GFX10_RBPLUS 1543 * RB = only for TILE_VER_GFX9 & DCC 1544 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) 1545 */ 1546 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 1547 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 1548 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 1549 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 1550 #define AMD_FMT_MOD_PACKERS_SHIFT 27 1551 #define AMD_FMT_MOD_PACKERS_MASK 0x7 1552 #define AMD_FMT_MOD_RB_SHIFT 30 1553 #define AMD_FMT_MOD_RB_MASK 0x7 1554 #define AMD_FMT_MOD_PIPE_SHIFT 33 1555 #define AMD_FMT_MOD_PIPE_MASK 0x7 1556 1557 #define AMD_FMT_MOD_SET(field, value) \ 1558 ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) 1559 #define AMD_FMT_MOD_GET(field, value) \ 1560 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) 1561 #define AMD_FMT_MOD_CLEAR(field) \ 1562 (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) 1563 1564 #if defined(__cplusplus) 1565 } 1566 #endif 1567 1568 #endif /* DRM_FOURCC_H */ 1569