1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 28 #if defined(__cplusplus) 29 extern "C" { 30 #endif 31 32 /** 33 * DOC: overview 34 * 35 * In the DRM subsystem, framebuffer pixel formats are described using the 36 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 37 * fourcc code, a Format Modifier may optionally be provided, in order to 38 * further describe the buffer's format - for example tiling or compression. 39 * 40 * Format Modifiers 41 * ---------------- 42 * 43 * Format modifiers are used in conjunction with a fourcc code, forming a 44 * unique fourcc:modifier pair. This format:modifier pair must fully define the 45 * format and data layout of the buffer, and should be the only way to describe 46 * that particular buffer. 47 * 48 * Having multiple fourcc:modifier pairs which describe the same layout should 49 * be avoided, as such aliases run the risk of different drivers exposing 50 * different names for the same data format, forcing userspace to understand 51 * that they are aliases. 52 * 53 * Format modifiers may change any property of the buffer, including the number 54 * of planes and/or the required allocation size. Format modifiers are 55 * vendor-namespaced, and as such the relationship between a fourcc code and a 56 * modifier is specific to the modifer being used. For example, some modifiers 57 * may preserve meaning - such as number of planes - from the fourcc code, 58 * whereas others may not. 59 * 60 * Modifiers must uniquely encode buffer layout. In other words, a buffer must 61 * match only a single modifier. A modifier must not be a subset of layouts of 62 * another modifier. For instance, it's incorrect to encode pitch alignment in 63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel 64 * aligned modifier. That said, modifiers can have implicit minimal 65 * requirements. 66 * 67 * For modifiers where the combination of fourcc code and modifier can alias, 68 * a canonical pair needs to be defined and used by all drivers. Preferred 69 * combinations are also encouraged where all combinations might lead to 70 * confusion and unnecessarily reduced interoperability. An example for the 71 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. 72 * 73 * There are two kinds of modifier users: 74 * 75 * - Kernel and user-space drivers: for drivers it's important that modifiers 76 * don't alias, otherwise two drivers might support the same format but use 77 * different aliases, preventing them from sharing buffers in an efficient 78 * format. 79 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users 80 * see modifiers as opaque tokens they can check for equality and intersect. 81 * These users musn't need to know to reason about the modifier value 82 * (i.e. they are not expected to extract information out of the modifier). 83 * 84 * Vendors should document their modifier usage in as much detail as 85 * possible, to ensure maximum compatibility across devices, drivers and 86 * applications. 87 * 88 * The authoritative list of format modifier codes is found in 89 * `include/uapi/drm/drm_fourcc.h` 90 */ 91 92 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ 93 ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) 94 95 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ 96 97 /* Reserve 0 for the invalid format specifier */ 98 #define DRM_FORMAT_INVALID 0 99 100 /* color index */ 101 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 102 103 /* 8 bpp Red */ 104 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 105 106 /* 10 bpp Red */ 107 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ 108 109 /* 12 bpp Red */ 110 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ 111 112 /* 16 bpp Red */ 113 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 114 115 /* 16 bpp RG */ 116 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 117 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 118 119 /* 32 bpp RG */ 120 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 121 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 122 123 /* 8 bpp RGB */ 124 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 125 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 126 127 /* 16 bpp RGB */ 128 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 129 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 130 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 131 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 132 133 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 134 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 135 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 136 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 137 138 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 139 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 140 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 141 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 142 143 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 144 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 145 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 146 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 147 148 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 149 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 150 151 /* 24 bpp RGB */ 152 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 153 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 154 155 /* 32 bpp RGB */ 156 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 157 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 158 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 159 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 160 161 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 162 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 163 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 164 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 165 166 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 167 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 168 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 169 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 170 171 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 172 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 173 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 174 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 175 176 /* 64 bpp RGB */ 177 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 178 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 179 180 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 181 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 182 183 /* 184 * Floating point 64bpp RGB 185 * IEEE 754-2008 binary16 half-precision float 186 * [15:0] sign:exponent:mantissa 1:5:10 187 */ 188 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 189 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 190 191 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 192 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 193 194 /* 195 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits 196 * of unused padding per component: 197 */ 198 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ 199 200 /* packed YCbCr */ 201 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 202 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 203 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 204 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 205 206 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 207 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 208 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ 209 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ 210 211 /* 212 * packed Y2xx indicate for each component, xx valid data occupy msb 213 * 16-xx padding occupy lsb 214 */ 215 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ 216 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ 217 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ 218 219 /* 220 * packed Y4xx indicate for each component, xx valid data occupy msb 221 * 16-xx padding occupy lsb except Y410 222 */ 223 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ 224 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 225 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ 226 227 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ 228 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 229 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ 230 231 /* 232 * packed YCbCr420 2x2 tiled formats 233 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 234 */ 235 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 236 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 237 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 238 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 239 240 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 241 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 242 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 243 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 244 245 /* 246 * 1-plane YUV 4:2:0 247 * In these formats, the component ordering is specified (Y, followed by U 248 * then V), but the exact Linear layout is undefined. 249 * These formats can only be used with a non-Linear modifier. 250 */ 251 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') 252 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') 253 254 /* 255 * 2 plane RGB + A 256 * index 0 = RGB plane, same format as the corresponding non _A8 format has 257 * index 1 = A plane, [7:0] A 258 */ 259 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 260 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 261 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 262 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 263 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 264 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 265 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 266 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 267 268 /* 269 * 2 plane YCbCr 270 * index 0 = Y plane, [7:0] Y 271 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 272 * or 273 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 274 */ 275 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 276 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 277 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 278 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 279 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 280 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 281 /* 282 * 2 plane YCbCr 283 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian 284 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian 285 */ 286 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ 287 288 /* 289 * 2 plane YCbCr MSB aligned 290 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 291 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 292 */ 293 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ 294 295 /* 296 * 2 plane YCbCr MSB aligned 297 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 298 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 299 */ 300 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ 301 302 /* 303 * 2 plane YCbCr MSB aligned 304 * index 0 = Y plane, [15:0] Y:x [12:4] little endian 305 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian 306 */ 307 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ 308 309 /* 310 * 2 plane YCbCr MSB aligned 311 * index 0 = Y plane, [15:0] Y little endian 312 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian 313 */ 314 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ 315 316 /* 2 plane YCbCr420. 317 * 3 10 bit components and 2 padding bits packed into 4 bytes. 318 * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian 319 * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian 320 */ 321 #define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */ 322 323 /* 3 plane non-subsampled (444) YCbCr 324 * 16 bits per component, but only 10 bits are used and 6 bits are padded 325 * index 0: Y plane, [15:0] Y:x [10:6] little endian 326 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian 327 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian 328 */ 329 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') 330 331 /* 3 plane non-subsampled (444) YCrCb 332 * 16 bits per component, but only 10 bits are used and 6 bits are padded 333 * index 0: Y plane, [15:0] Y:x [10:6] little endian 334 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian 335 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian 336 */ 337 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') 338 339 /* 340 * 3 plane YCbCr 341 * index 0: Y plane, [7:0] Y 342 * index 1: Cb plane, [7:0] Cb 343 * index 2: Cr plane, [7:0] Cr 344 * or 345 * index 1: Cr plane, [7:0] Cr 346 * index 2: Cb plane, [7:0] Cb 347 */ 348 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 349 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 350 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 351 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 352 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 353 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 354 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 355 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 356 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 357 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 358 359 360 /* 361 * Format Modifiers: 362 * 363 * Format modifiers describe, typically, a re-ordering or modification 364 * of the data in a plane of an FB. This can be used to express tiled/ 365 * swizzled formats, or compression, or a combination of the two. 366 * 367 * The upper 8 bits of the format modifier are a vendor-id as assigned 368 * below. The lower 56 bits are assigned as vendor sees fit. 369 */ 370 371 /* Vendor Ids: */ 372 #define DRM_FORMAT_MOD_VENDOR_NONE 0 373 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 374 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 375 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 376 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 377 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 378 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 379 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 380 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 381 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 382 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a 383 384 /* add more to the end as needed */ 385 386 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 387 388 #define fourcc_mod_get_vendor(modifier) \ 389 (((modifier) >> 56) & 0xff) 390 391 #define fourcc_mod_is_vendor(modifier, vendor) \ 392 (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) 393 394 #define fourcc_mod_code(vendor, val) \ 395 ((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 396 397 /* 398 * Format Modifier tokens: 399 * 400 * When adding a new token please document the layout with a code comment, 401 * similar to the fourcc codes above. drm_fourcc.h is considered the 402 * authoritative source for all of these. 403 * 404 * Generic modifier names: 405 * 406 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names 407 * for layouts which are common across multiple vendors. To preserve 408 * compatibility, in cases where a vendor-specific definition already exists and 409 * a generic name for it is desired, the common name is a purely symbolic alias 410 * and must use the same numerical value as the original definition. 411 * 412 * Note that generic names should only be used for modifiers which describe 413 * generic layouts (such as pixel re-ordering), which may have 414 * independently-developed support across multiple vendors. 415 * 416 * In future cases where a generic layout is identified before merging with a 417 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor 418 * 'NONE' could be considered. This should only be for obvious, exceptional 419 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only 420 * apply to a single vendor. 421 * 422 * Generic names should not be used for cases where multiple hardware vendors 423 * have implementations of the same standardised compression scheme (such as 424 * AFBC). In those cases, all implementations should use the same format 425 * modifier(s), reflecting the vendor of the standard. 426 */ 427 428 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE 429 430 /* 431 * Invalid Modifier 432 * 433 * This modifier can be used as a sentinel to terminate the format modifiers 434 * list, or to initialize a variable with an invalid modifier. It might also be 435 * used to report an error back to userspace for certain APIs. 436 */ 437 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 438 439 /* 440 * Linear Layout 441 * 442 * Just plain linear layout. Note that this is different from no specifying any 443 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 444 * which tells the driver to also take driver-internal information into account 445 * and so might actually result in a tiled framebuffer. 446 */ 447 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 448 449 /* 450 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead 451 * 452 * The "none" format modifier doesn't actually mean that the modifier is 453 * implicit, instead it means that the layout is linear. Whether modifiers are 454 * used is out-of-band information carried in an API-specific way (e.g. in a 455 * flag for drm_mode_fb_cmd2). 456 */ 457 #define DRM_FORMAT_MOD_NONE 0 458 459 /* Intel framebuffer modifiers */ 460 461 /* 462 * Intel X-tiling layout 463 * 464 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 465 * in row-major layout. Within the tile bytes are laid out row-major, with 466 * a platform-dependent stride. On top of that the memory can apply 467 * platform-depending swizzling of some higher address bits into bit6. 468 * 469 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 470 * On earlier platforms the is highly platforms specific and not useful for 471 * cross-driver sharing. It exists since on a given platform it does uniquely 472 * identify the layout in a simple way for i915-specific userspace, which 473 * facilitated conversion of userspace to modifiers. Additionally the exact 474 * format on some really old platforms is not known. 475 */ 476 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 477 478 /* 479 * Intel Y-tiling layout 480 * 481 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 482 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 483 * chunks column-major, with a platform-dependent height. On top of that the 484 * memory can apply platform-depending swizzling of some higher address bits 485 * into bit6. 486 * 487 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 488 * On earlier platforms the is highly platforms specific and not useful for 489 * cross-driver sharing. It exists since on a given platform it does uniquely 490 * identify the layout in a simple way for i915-specific userspace, which 491 * facilitated conversion of userspace to modifiers. Additionally the exact 492 * format on some really old platforms is not known. 493 */ 494 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 495 496 /* 497 * Intel Yf-tiling layout 498 * 499 * This is a tiled layout using 4Kb tiles in row-major layout. 500 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 501 * are arranged in four groups (two wide, two high) with column-major layout. 502 * Each group therefore consits out of four 256 byte units, which are also laid 503 * out as 2x2 column-major. 504 * 256 byte units are made out of four 64 byte blocks of pixels, producing 505 * either a square block or a 2:1 unit. 506 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 507 * in pixel depends on the pixel depth. 508 */ 509 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 510 511 /* 512 * Intel color control surface (CCS) for render compression 513 * 514 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 515 * The main surface will be plane index 0 and must be Y/Yf-tiled, 516 * the CCS will be plane index 1. 517 * 518 * Each CCS tile matches a 1024x512 pixel area of the main surface. 519 * To match certain aspects of the 3D hardware the CCS is 520 * considered to be made up of normal 128Bx32 Y tiles, Thus 521 * the CCS pitch must be specified in multiples of 128 bytes. 522 * 523 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 524 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 525 * But that fact is not relevant unless the memory is accessed 526 * directly. 527 */ 528 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 529 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 530 531 /* 532 * Intel color control surfaces (CCS) for Gen-12 render compression. 533 * 534 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 535 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 536 * main surface. In other words, 4 bits in CCS map to a main surface cache 537 * line pair. The main surface pitch is required to be a multiple of four 538 * Y-tile widths. 539 */ 540 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) 541 542 /* 543 * Intel color control surfaces (CCS) for Gen-12 media compression 544 * 545 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 546 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 547 * main surface. In other words, 4 bits in CCS map to a main surface cache 548 * line pair. The main surface pitch is required to be a multiple of four 549 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the 550 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 551 * planes 2 and 3 for the respective CCS. 552 */ 553 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) 554 555 /* 556 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render 557 * compression. 558 * 559 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear 560 * and at index 1. The clear color is stored at index 2, and the pitch should 561 * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits 562 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 563 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 564 * the converted clear color of size 64 bits. The first 32 bits store the Lower 565 * Converted Clear Color value and the next 32 bits store the Higher Converted 566 * Clear Color value when applicable. The Converted Clear Color values are 567 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 568 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 569 * corresponds to an area of 4x1 tiles in the main surface. The main surface 570 * pitch is required to be a multiple of 4 tile widths. 571 */ 572 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) 573 574 /* 575 * Intel Tile 4 layout 576 * 577 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same 578 * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It 579 * only differs from Tile Y at the 256B granularity in between. At this 580 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape 581 * of 64B x 8 rows. 582 */ 583 #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) 584 585 /* 586 * Intel color control surfaces (CCS) for DG2 render compression. 587 * 588 * The main surface is Tile 4 and at plane index 0. The CCS data is stored 589 * outside of the GEM object in a reserved memory area dedicated for the 590 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The 591 * main surface pitch is required to be a multiple of four Tile 4 widths. 592 */ 593 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10) 594 595 /* 596 * Intel color control surfaces (CCS) for DG2 media compression. 597 * 598 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 599 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 600 * 0 and 1, respectively. The CCS for all planes are stored outside of the 601 * GEM object in a reserved memory area dedicated for the storage of the 602 * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface 603 * pitch is required to be a multiple of four Tile 4 widths. 604 */ 605 #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11) 606 607 /* 608 * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression. 609 * 610 * The main surface is Tile 4 and at plane index 0. The CCS data is stored 611 * outside of the GEM object in a reserved memory area dedicated for the 612 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The 613 * main surface pitch is required to be a multiple of four Tile 4 widths. The 614 * clear color is stored at plane index 1 and the pitch should be 64 bytes 615 * aligned. The format of the 256 bits of clear color data matches the one used 616 * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description 617 * for details. 618 */ 619 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) 620 621 /* 622 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 623 * 624 * Macroblocks are laid in a Z-shape, and each pixel data is following the 625 * standard NV12 style. 626 * As for NV12, an image is the result of two frame buffers: one for Y, 627 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 628 * Alignment requirements are (for each buffer): 629 * - multiple of 128 pixels for the width 630 * - multiple of 32 pixels for the height 631 * 632 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 633 */ 634 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 635 636 /* 637 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 638 * 639 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 640 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 641 * they correspond to their 16x16 luma block. 642 */ 643 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 644 645 /* 646 * Qualcomm Compressed Format 647 * 648 * Refers to a compressed variant of the base format that is compressed. 649 * Implementation may be platform and base-format specific. 650 * 651 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 652 * Pixel data pitch/stride is aligned with macrotile width. 653 * Pixel data height is aligned with macrotile height. 654 * Entire pixel data buffer is aligned with 4k(bytes). 655 */ 656 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 657 658 /* 659 * Qualcomm Tiled Format 660 * 661 * Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed. 662 * Implementation may be platform and base-format specific. 663 * 664 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 665 * Pixel data pitch/stride is aligned with macrotile width. 666 * Pixel data height is aligned with macrotile height. 667 * Entire pixel data buffer is aligned with 4k(bytes). 668 */ 669 #define DRM_FORMAT_MOD_QCOM_TILED3 fourcc_mod_code(QCOM, 3) 670 671 /* 672 * Qualcomm Alternate Tiled Format 673 * 674 * Alternate tiled format typically only used within GMEM. 675 * Implementation may be platform and base-format specific. 676 */ 677 #define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2) 678 679 680 /* Vivante framebuffer modifiers */ 681 682 /* 683 * Vivante 4x4 tiling layout 684 * 685 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 686 * layout. 687 */ 688 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 689 690 /* 691 * Vivante 64x64 super-tiling layout 692 * 693 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 694 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 695 * major layout. 696 * 697 * For more information: see 698 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 699 */ 700 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 701 702 /* 703 * Vivante 4x4 tiling layout for dual-pipe 704 * 705 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 706 * different base address. Offsets from the base addresses are therefore halved 707 * compared to the non-split tiled layout. 708 */ 709 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 710 711 /* 712 * Vivante 64x64 super-tiling layout for dual-pipe 713 * 714 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 715 * starts at a different base address. Offsets from the base addresses are 716 * therefore halved compared to the non-split super-tiled layout. 717 */ 718 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 719 720 /* NVIDIA frame buffer modifiers */ 721 722 /* 723 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 724 * 725 * Pixels are arranged in simple tiles of 16 x 16 bytes. 726 */ 727 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 728 729 /* 730 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, 731 * and Tegra GPUs starting with Tegra K1. 732 * 733 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies 734 * based on the architecture generation. GOBs themselves are then arranged in 735 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power 736 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents 737 * a block depth or height of "4"). 738 * 739 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 740 * in full detail. 741 * 742 * Macro 743 * Bits Param Description 744 * ---- ----- ----------------------------------------------------------------- 745 * 746 * 3:0 h log2(height) of each block, in GOBs. Placed here for 747 * compatibility with the existing 748 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 749 * 750 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for 751 * compatibility with the existing 752 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 753 * 754 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block 755 * size). Must be zero. 756 * 757 * Note there is no log2(width) parameter. Some portions of the 758 * hardware support a block width of two gobs, but it is impractical 759 * to use due to lack of support elsewhere, and has no known 760 * benefits. 761 * 762 * 11:9 - Reserved (To support 2D-array textures with variable array stride 763 * in blocks, specified via log2(tile width in blocks)). Must be 764 * zero. 765 * 766 * 19:12 k Page Kind. This value directly maps to a field in the page 767 * tables of all GPUs >= NV50. It affects the exact layout of bits 768 * in memory and can be derived from the tuple 769 * 770 * (format, GPU model, compression type, samples per pixel) 771 * 772 * Where compression type is defined below. If GPU model were 773 * implied by the format modifier, format, or memory buffer, page 774 * kind would not need to be included in the modifier itself, but 775 * since the modifier should define the layout of the associated 776 * memory buffer independent from any device or other context, it 777 * must be included here. 778 * 779 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed 780 * starting with Fermi GPUs. Additionally, the mapping between page 781 * kind and bit layout has changed at various points. 782 * 783 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping 784 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping 785 * 2 = Gob Height 8, Turing+ Page Kind mapping 786 * 3 = Reserved for future use. 787 * 788 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 789 * bit remapping step that occurs at an even lower level than the 790 * page kind and block linear swizzles. This causes the layout of 791 * surfaces mapped in those SOC's GPUs to be incompatible with the 792 * equivalent mapping on other GPUs in the same system. 793 * 794 * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 795 * 1 = Desktop GPU and Tegra Xavier+ Layout 796 * 797 * 25:23 c Lossless Framebuffer Compression type. 798 * 799 * 0 = none 800 * 1 = ROP/3D, layout 1, exact compression format implied by Page 801 * Kind field 802 * 2 = ROP/3D, layout 2, exact compression format implied by Page 803 * Kind field 804 * 3 = CDE horizontal 805 * 4 = CDE vertical 806 * 5 = Reserved for future use 807 * 6 = Reserved for future use 808 * 7 = Reserved for future use 809 * 810 * 55:25 - Reserved for future use. Must be zero. 811 */ 812 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 813 fourcc_mod_code(NVIDIA, (0x10 | \ 814 ((h) & 0xf) | \ 815 (((k) & 0xff) << 12) | \ 816 (((g) & 0x3) << 20) | \ 817 (((s) & 0x1) << 22) | \ 818 (((c) & 0x7) << 23))) 819 820 /* To grandfather in prior block linear format modifiers to the above layout, 821 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable 822 * with block-linear layouts, is remapped within drivers to the value 0xfe, 823 * which corresponds to the "generic" kind used for simple single-sample 824 * uncompressed color formats on Fermi - Volta GPUs. 825 */ 826 static inline uint64_t 827 drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier) 828 { 829 if (!(modifier & 0x10) || (modifier & (0xff << 12))) 830 return modifier; 831 else 832 return modifier | (0xfe << 12); 833 } 834 835 /* 836 * 16Bx2 Block Linear layout, used by Tegra K1 and later 837 * 838 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 839 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 840 * 841 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 842 * 843 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 844 * Valid values are: 845 * 846 * 0 == ONE_GOB 847 * 1 == TWO_GOBS 848 * 2 == FOUR_GOBS 849 * 3 == EIGHT_GOBS 850 * 4 == SIXTEEN_GOBS 851 * 5 == THIRTYTWO_GOBS 852 * 853 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 854 * in full detail. 855 */ 856 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 857 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) 858 859 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 860 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) 861 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 862 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) 863 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 864 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) 865 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 866 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) 867 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 868 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) 869 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 870 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) 871 872 /* 873 * Some Broadcom modifiers take parameters, for example the number of 874 * vertical lines in the image. Reserve the lower 32 bits for modifier 875 * type, and the next 24 bits for parameters. Top 8 bits are the 876 * vendor code. 877 */ 878 #define __fourcc_mod_broadcom_param_shift 8 879 #define __fourcc_mod_broadcom_param_bits 48 880 #define fourcc_mod_broadcom_code(val, params) \ 881 fourcc_mod_code(BROADCOM, ((((uint64_t)params) << __fourcc_mod_broadcom_param_shift) | val)) 882 #define fourcc_mod_broadcom_param(m) \ 883 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 884 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 885 #define fourcc_mod_broadcom_mod(m) \ 886 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 887 __fourcc_mod_broadcom_param_shift)) 888 889 /* 890 * Broadcom VC4 "T" format 891 * 892 * This is the primary layout that the V3D GPU can texture from (it 893 * can't do linear). The T format has: 894 * 895 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 896 * pixels at 32 bit depth. 897 * 898 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 899 * 16x16 pixels). 900 * 901 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 902 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 903 * they're (TR, BR, BL, TL), where bottom left is start of memory. 904 * 905 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 906 * tiles) or right-to-left (odd rows of 4k tiles). 907 */ 908 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 909 910 /* 911 * Broadcom SAND format 912 * 913 * This is the native format that the H.264 codec block uses. For VC4 914 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 915 * 916 * The image can be considered to be split into columns, and the 917 * columns are placed consecutively into memory. The width of those 918 * columns can be either 32, 64, 128, or 256 pixels, but in practice 919 * only 128 pixel columns are used. 920 * 921 * The pitch between the start of each column is set to optimally 922 * switch between SDRAM banks. This is passed as the number of lines 923 * of column width in the modifier (we can't use the stride value due 924 * to various core checks that look at it , so you should set the 925 * stride to width*cpp). 926 * 927 * Note that the column height for this format modifier is the same 928 * for all of the planes, assuming that each column contains both Y 929 * and UV. Some SAND-using hardware stores UV in a separate tiled 930 * image from Y to reduce the column height, which is not supported 931 * with these modifiers. 932 * 933 * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also 934 * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes 935 * wide, but as this is a 10 bpp format that translates to 96 pixels. 936 */ 937 938 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 939 fourcc_mod_broadcom_code(2, v) 940 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 941 fourcc_mod_broadcom_code(3, v) 942 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 943 fourcc_mod_broadcom_code(4, v) 944 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 945 fourcc_mod_broadcom_code(5, v) 946 947 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 948 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 949 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 950 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 951 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 952 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 953 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 954 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 955 956 /* Broadcom UIF format 957 * 958 * This is the common format for the current Broadcom multimedia 959 * blocks, including V3D 3.x and newer, newer video codecs, and 960 * displays. 961 * 962 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 963 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 964 * stored in columns, with padding between the columns to ensure that 965 * moving from one column to the next doesn't hit the same SDRAM page 966 * bank. 967 * 968 * To calculate the padding, it is assumed that each hardware block 969 * and the software driving it knows the platform's SDRAM page size, 970 * number of banks, and XOR address, and that it's identical between 971 * all blocks using the format. This tiling modifier will use XOR as 972 * necessary to reduce the padding. If a hardware block can't do XOR, 973 * the assumption is that a no-XOR tiling modifier will be created. 974 */ 975 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 976 977 /* 978 * Arm Framebuffer Compression (AFBC) modifiers 979 * 980 * AFBC is a proprietary lossless image compression protocol and format. 981 * It provides fine-grained random access and minimizes the amount of data 982 * transferred between IP blocks. 983 * 984 * AFBC has several features which may be supported and/or used, which are 985 * represented using bits in the modifier. Not all combinations are valid, 986 * and different devices or use-cases may support different combinations. 987 * 988 * Further information on the use of AFBC modifiers can be found in 989 * Documentation/gpu/afbc.rst 990 */ 991 992 /* 993 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific 994 * modifiers) denote the category for modifiers. Currently we have three 995 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of 996 * sixteen different categories. 997 */ 998 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ 999 fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) 1000 1001 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 1002 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 1003 1004 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ 1005 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) 1006 1007 /* 1008 * AFBC superblock size 1009 * 1010 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 1011 * size (in pixels) must be aligned to a multiple of the superblock size. 1012 * Four lowest significant bits(LSBs) are reserved for block size. 1013 * 1014 * Where one superblock size is specified, it applies to all planes of the 1015 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, 1016 * the first applies to the Luma plane and the second applies to the Chroma 1017 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). 1018 * Multiple superblock sizes are only valid for multi-plane YCbCr formats. 1019 */ 1020 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 1021 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 1022 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 1023 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) 1024 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) 1025 1026 /* 1027 * AFBC lossless colorspace transform 1028 * 1029 * Indicates that the buffer makes use of the AFBC lossless colorspace 1030 * transform. 1031 */ 1032 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 1033 1034 /* 1035 * AFBC block-split 1036 * 1037 * Indicates that the payload of each superblock is split. The second 1038 * half of the payload is positioned at a predefined offset from the start 1039 * of the superblock payload. 1040 */ 1041 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 1042 1043 /* 1044 * AFBC sparse layout 1045 * 1046 * This flag indicates that the payload of each superblock must be stored at a 1047 * predefined position relative to the other superblocks in the same AFBC 1048 * buffer. This order is the same order used by the header buffer. In this mode 1049 * each superblock is given the same amount of space as an uncompressed 1050 * superblock of the particular format would require, rounding up to the next 1051 * multiple of 128 bytes in size. 1052 */ 1053 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 1054 1055 /* 1056 * AFBC copy-block restrict 1057 * 1058 * Buffers with this flag must obey the copy-block restriction. The restriction 1059 * is such that there are no copy-blocks referring across the border of 8x8 1060 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 1061 */ 1062 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 1063 1064 /* 1065 * AFBC tiled layout 1066 * 1067 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 1068 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 1069 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 1070 * larger bpp formats. The order between the tiles is scan line. 1071 * When the tiled layout is used, the buffer size (in pixels) must be aligned 1072 * to the tile size. 1073 */ 1074 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 1075 1076 /* 1077 * AFBC solid color blocks 1078 * 1079 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 1080 * can be reduced if a whole superblock is a single color. 1081 */ 1082 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 1083 1084 /* 1085 * AFBC double-buffer 1086 * 1087 * Indicates that the buffer is allocated in a layout safe for front-buffer 1088 * rendering. 1089 */ 1090 #define AFBC_FORMAT_MOD_DB (1ULL << 10) 1091 1092 /* 1093 * AFBC buffer content hints 1094 * 1095 * Indicates that the buffer includes per-superblock content hints. 1096 */ 1097 #define AFBC_FORMAT_MOD_BCH (1ULL << 11) 1098 1099 /* AFBC uncompressed storage mode 1100 * 1101 * Indicates that the buffer is using AFBC uncompressed storage mode. 1102 * In this mode all superblock payloads in the buffer use the uncompressed 1103 * storage mode, which is usually only used for data which cannot be compressed. 1104 * The buffer layout is the same as for AFBC buffers without USM set, this only 1105 * affects the storage mode of the individual superblocks. Note that even a 1106 * buffer without USM set may use uncompressed storage mode for some or all 1107 * superblocks, USM just guarantees it for all. 1108 */ 1109 #define AFBC_FORMAT_MOD_USM (1ULL << 12) 1110 1111 /* 1112 * Arm Fixed-Rate Compression (AFRC) modifiers 1113 * 1114 * AFRC is a proprietary fixed rate image compression protocol and format, 1115 * designed to provide guaranteed bandwidth and memory footprint 1116 * reductions in graphics and media use-cases. 1117 * 1118 * AFRC buffers consist of one or more planes, with the same components 1119 * and meaning as an uncompressed buffer using the same pixel format. 1120 * 1121 * Within each plane, the pixel/luma/chroma values are grouped into 1122 * "coding unit" blocks which are individually compressed to a 1123 * fixed size (in bytes). All coding units within a given plane of a buffer 1124 * store the same number of values, and have the same compressed size. 1125 * 1126 * The coding unit size is configurable, allowing different rates of compression. 1127 * 1128 * The start of each AFRC buffer plane must be aligned to an alignment granule which 1129 * depends on the coding unit size. 1130 * 1131 * Coding Unit Size Plane Alignment 1132 * ---------------- --------------- 1133 * 16 bytes 1024 bytes 1134 * 24 bytes 512 bytes 1135 * 32 bytes 2048 bytes 1136 * 1137 * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned 1138 * to a multiple of the paging tile dimensions. 1139 * The dimensions of each paging tile depend on whether the buffer is optimised for 1140 * scanline (SCAN layout) or rotated (ROT layout) access. 1141 * 1142 * Layout Paging Tile Width Paging Tile Height 1143 * ------ ----------------- ------------------ 1144 * SCAN 16 coding units 4 coding units 1145 * ROT 8 coding units 8 coding units 1146 * 1147 * The dimensions of each coding unit depend on the number of components 1148 * in the compressed plane and whether the buffer is optimised for 1149 * scanline (SCAN layout) or rotated (ROT layout) access. 1150 * 1151 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height 1152 * ----------------------------- --------- ----------------- ------------------ 1153 * 1 SCAN 16 samples 4 samples 1154 * Example: 16x4 luma samples in a 'Y' plane 1155 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1156 * ----------------------------- --------- ----------------- ------------------ 1157 * 1 ROT 8 samples 8 samples 1158 * Example: 8x8 luma samples in a 'Y' plane 1159 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1160 * ----------------------------- --------- ----------------- ------------------ 1161 * 2 DONT CARE 8 samples 4 samples 1162 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer 1163 * ----------------------------- --------- ----------------- ------------------ 1164 * 3 DONT CARE 4 samples 4 samples 1165 * Example: 4x4 pixels in an RGB buffer without alpha 1166 * ----------------------------- --------- ----------------- ------------------ 1167 * 4 DONT CARE 4 samples 4 samples 1168 * Example: 4x4 pixels in an RGB buffer with alpha 1169 */ 1170 1171 #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 1172 1173 #define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ 1174 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) 1175 1176 /* 1177 * AFRC coding unit size modifier. 1178 * 1179 * Indicates the number of bytes used to store each compressed coding unit for 1180 * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance 1181 * is the same for both Cb and Cr, which may be stored in separate planes. 1182 * 1183 * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store 1184 * each compressed coding unit in the first plane of the buffer. For RGBA buffers 1185 * this is the only plane, while for semi-planar and fully-planar YUV buffers, 1186 * this corresponds to the luma plane. 1187 * 1188 * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store 1189 * each compressed coding unit in the second and third planes in the buffer. 1190 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s). 1191 * 1192 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified 1193 * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero. 1194 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and 1195 * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified. 1196 */ 1197 #define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf 1198 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL) 1199 #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL) 1200 #define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL) 1201 1202 #define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size) 1203 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4) 1204 1205 /* 1206 * AFRC scanline memory layout. 1207 * 1208 * Indicates if the buffer uses the scanline-optimised layout 1209 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout. 1210 * The memory layout is the same for all planes. 1211 */ 1212 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) 1213 1214 /* 1215 * Arm 16x16 Block U-Interleaved modifier 1216 * 1217 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image 1218 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels 1219 * in the block are reordered. 1220 */ 1221 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ 1222 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) 1223 1224 /* 1225 * Allwinner tiled modifier 1226 * 1227 * This tiling mode is implemented by the VPU found on all Allwinner platforms, 1228 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 1229 * planes. 1230 * 1231 * With this tiling, the luminance samples are disposed in tiles representing 1232 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. 1233 * The pixel order in each tile is linear and the tiles are disposed linearly, 1234 * both in row-major order. 1235 */ 1236 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) 1237 1238 /* 1239 * Amlogic Video Framebuffer Compression modifiers 1240 * 1241 * Amlogic uses a proprietary lossless image compression protocol and format 1242 * for their hardware video codec accelerators, either video decoders or 1243 * video input encoders. 1244 * 1245 * It considerably reduces memory bandwidth while writing and reading 1246 * frames in memory. 1247 * 1248 * The underlying storage is considered to be 3 components, 8bit or 10-bit 1249 * per component YCbCr 420, single plane : 1250 * - DRM_FORMAT_YUV420_8BIT 1251 * - DRM_FORMAT_YUV420_10BIT 1252 * 1253 * The first 8 bits of the mode defines the layout, then the following 8 bits 1254 * defines the options changing the layout. 1255 * 1256 * Not all combinations are valid, and different SoCs may support different 1257 * combinations of layout and options. 1258 */ 1259 #define __fourcc_mod_amlogic_layout_mask 0xff 1260 #define __fourcc_mod_amlogic_options_shift 8 1261 #define __fourcc_mod_amlogic_options_mask 0xff 1262 1263 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ 1264 fourcc_mod_code(AMLOGIC, \ 1265 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ 1266 (((__options) & __fourcc_mod_amlogic_options_mask) \ 1267 << __fourcc_mod_amlogic_options_shift)) 1268 1269 /* Amlogic FBC Layouts */ 1270 1271 /* 1272 * Amlogic FBC Basic Layout 1273 * 1274 * The basic layout is composed of: 1275 * - a body content organized in 64x32 superblocks with 4096 bytes per 1276 * superblock in default mode. 1277 * - a 32 bytes per 128x64 header block 1278 * 1279 * This layout is transferrable between Amlogic SoCs supporting this modifier. 1280 */ 1281 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) 1282 1283 /* 1284 * Amlogic FBC Scatter Memory layout 1285 * 1286 * Indicates the header contains IOMMU references to the compressed 1287 * frames content to optimize memory access and layout. 1288 * 1289 * In this mode, only the header memory address is needed, thus the 1290 * content memory organization is tied to the current producer 1291 * execution and cannot be saved/dumped neither transferrable between 1292 * Amlogic SoCs supporting this modifier. 1293 * 1294 * Due to the nature of the layout, these buffers are not expected to 1295 * be accessible by the user-space clients, but only accessible by the 1296 * hardware producers and consumers. 1297 * 1298 * The user-space clients should expect a failure while trying to mmap 1299 * the DMA-BUF handle returned by the producer. 1300 */ 1301 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) 1302 1303 /* Amlogic FBC Layout Options Bit Mask */ 1304 1305 /* 1306 * Amlogic FBC Memory Saving mode 1307 * 1308 * Indicates the storage is packed when pixel size is multiple of word 1309 * boudaries, i.e. 8bit should be stored in this mode to save allocation 1310 * memory. 1311 * 1312 * This mode reduces body layout to 3072 bytes per 64x32 superblock with 1313 * the basic layout and 3200 bytes per 64x32 superblock combined with 1314 * the scatter layout. 1315 */ 1316 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) 1317 1318 /* 1319 * AMD modifiers 1320 * 1321 * Memory layout: 1322 * 1323 * without DCC: 1324 * - main surface 1325 * 1326 * with DCC & without DCC_RETILE: 1327 * - main surface in plane 0 1328 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) 1329 * 1330 * with DCC & DCC_RETILE: 1331 * - main surface in plane 0 1332 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) 1333 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) 1334 * 1335 * For multi-plane formats the above surfaces get merged into one plane for 1336 * each format plane, based on the required alignment only. 1337 * 1338 * Bits Parameter Notes 1339 * ----- ------------------------ --------------------------------------------- 1340 * 1341 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* 1342 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* 1343 * 13 DCC 1344 * 14 DCC_RETILE 1345 * 15 DCC_PIPE_ALIGN 1346 * 16 DCC_INDEPENDENT_64B 1347 * 17 DCC_INDEPENDENT_128B 1348 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* 1349 * 20 DCC_CONSTANT_ENCODE 1350 * 23:21 PIPE_XOR_BITS Only for some chips 1351 * 26:24 BANK_XOR_BITS Only for some chips 1352 * 29:27 PACKERS Only for some chips 1353 * 32:30 RB Only for some chips 1354 * 35:33 PIPE Only for some chips 1355 * 55:36 - Reserved for future use, must be zero 1356 */ 1357 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) 1358 1359 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) 1360 1361 /* Reserve 0 for GFX8 and older */ 1362 #define AMD_FMT_MOD_TILE_VER_GFX9 1 1363 #define AMD_FMT_MOD_TILE_VER_GFX10 2 1364 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 1365 #define AMD_FMT_MOD_TILE_VER_GFX11 4 1366 1367 /* 1368 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical 1369 * version. 1370 */ 1371 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9 1372 1373 /* 1374 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has 1375 * GFX9 as canonical version. 1376 */ 1377 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 1378 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 1379 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 1380 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 1381 #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 1382 1383 #define AMD_FMT_MOD_DCC_BLOCK_64B 0 1384 #define AMD_FMT_MOD_DCC_BLOCK_128B 1 1385 #define AMD_FMT_MOD_DCC_BLOCK_256B 2 1386 1387 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 1388 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF 1389 #define AMD_FMT_MOD_TILE_SHIFT 8 1390 #define AMD_FMT_MOD_TILE_MASK 0x1F 1391 1392 /* Whether DCC compression is enabled. */ 1393 #define AMD_FMT_MOD_DCC_SHIFT 13 1394 #define AMD_FMT_MOD_DCC_MASK 0x1 1395 1396 /* 1397 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and 1398 * one which is not-aligned. 1399 */ 1400 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 1401 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 1402 1403 /* Only set if DCC_RETILE = false */ 1404 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 1405 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 1406 1407 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 1408 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 1409 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 1410 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 1411 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 1412 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 1413 1414 /* 1415 * DCC supports embedding some clear colors directly in the DCC surface. 1416 * However, on older GPUs the rendering HW ignores the embedded clear color 1417 * and prefers the driver provided color. This necessitates doing a fastclear 1418 * eliminate operation before a process transfers control. 1419 * 1420 * If this bit is set that means the fastclear eliminate is not needed for these 1421 * embeddable colors. 1422 */ 1423 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 1424 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 1425 1426 /* 1427 * The below fields are for accounting for per GPU differences. These are only 1428 * relevant for GFX9 and later and if the tile field is *_X/_T. 1429 * 1430 * PIPE_XOR_BITS = always needed 1431 * BANK_XOR_BITS = only for TILE_VER_GFX9 1432 * PACKERS = only for TILE_VER_GFX10_RBPLUS 1433 * RB = only for TILE_VER_GFX9 & DCC 1434 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) 1435 */ 1436 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 1437 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 1438 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 1439 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 1440 #define AMD_FMT_MOD_PACKERS_SHIFT 27 1441 #define AMD_FMT_MOD_PACKERS_MASK 0x7 1442 #define AMD_FMT_MOD_RB_SHIFT 30 1443 #define AMD_FMT_MOD_RB_MASK 0x7 1444 #define AMD_FMT_MOD_PIPE_SHIFT 33 1445 #define AMD_FMT_MOD_PIPE_MASK 0x7 1446 1447 #define AMD_FMT_MOD_SET(field, value) \ 1448 ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) 1449 #define AMD_FMT_MOD_GET(field, value) \ 1450 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) 1451 #define AMD_FMT_MOD_CLEAR(field) \ 1452 (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) 1453 1454 #if defined(__cplusplus) 1455 } 1456 #endif 1457 1458 #endif /* DRM_FOURCC_H */ 1459