1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 28 #if defined(__cplusplus) 29 extern "C" { 30 #endif 31 32 /** 33 * DOC: overview 34 * 35 * In the DRM subsystem, framebuffer pixel formats are described using the 36 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 37 * fourcc code, a Format Modifier may optionally be provided, in order to 38 * further describe the buffer's format - for example tiling or compression. 39 * 40 * Format Modifiers 41 * ---------------- 42 * 43 * Format modifiers are used in conjunction with a fourcc code, forming a 44 * unique fourcc:modifier pair. This format:modifier pair must fully define the 45 * format and data layout of the buffer, and should be the only way to describe 46 * that particular buffer. 47 * 48 * Having multiple fourcc:modifier pairs which describe the same layout should 49 * be avoided, as such aliases run the risk of different drivers exposing 50 * different names for the same data format, forcing userspace to understand 51 * that they are aliases. 52 * 53 * Format modifiers may change any property of the buffer, including the number 54 * of planes and/or the required allocation size. Format modifiers are 55 * vendor-namespaced, and as such the relationship between a fourcc code and a 56 * modifier is specific to the modifer being used. For example, some modifiers 57 * may preserve meaning - such as number of planes - from the fourcc code, 58 * whereas others may not. 59 * 60 * Modifiers must uniquely encode buffer layout. In other words, a buffer must 61 * match only a single modifier. A modifier must not be a subset of layouts of 62 * another modifier. For instance, it's incorrect to encode pitch alignment in 63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel 64 * aligned modifier. That said, modifiers can have implicit minimal 65 * requirements. 66 * 67 * For modifiers where the combination of fourcc code and modifier can alias, 68 * a canonical pair needs to be defined and used by all drivers. Preferred 69 * combinations are also encouraged where all combinations might lead to 70 * confusion and unnecessarily reduced interoperability. An example for the 71 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. 72 * 73 * There are two kinds of modifier users: 74 * 75 * - Kernel and user-space drivers: for drivers it's important that modifiers 76 * don't alias, otherwise two drivers might support the same format but use 77 * different aliases, preventing them from sharing buffers in an efficient 78 * format. 79 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users 80 * see modifiers as opaque tokens they can check for equality and intersect. 81 * These users musn't need to know to reason about the modifier value 82 * (i.e. they are not expected to extract information out of the modifier). 83 * 84 * Vendors should document their modifier usage in as much detail as 85 * possible, to ensure maximum compatibility across devices, drivers and 86 * applications. 87 * 88 * The authoritative list of format modifier codes is found in 89 * `include/uapi/drm/drm_fourcc.h` 90 */ 91 92 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ 93 ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) 94 95 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ 96 97 /* Reserve 0 for the invalid format specifier */ 98 #define DRM_FORMAT_INVALID 0 99 100 /* color index */ 101 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 102 103 /* 8 bpp Red */ 104 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 105 106 /* 10 bpp Red */ 107 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ 108 109 /* 12 bpp Red */ 110 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ 111 112 /* 16 bpp Red */ 113 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 114 115 /* 16 bpp RG */ 116 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 117 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 118 119 /* 32 bpp RG */ 120 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 121 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 122 123 /* 8 bpp RGB */ 124 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 125 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 126 127 /* 16 bpp RGB */ 128 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 129 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 130 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 131 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 132 133 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 134 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 135 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 136 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 137 138 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 139 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 140 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 141 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 142 143 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 144 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 145 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 146 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 147 148 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 149 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 150 151 /* 24 bpp RGB */ 152 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 153 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 154 155 /* 32 bpp RGB */ 156 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 157 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 158 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 159 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 160 161 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 162 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 163 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 164 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 165 166 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 167 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 168 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 169 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 170 171 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 172 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 173 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 174 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 175 176 /* 64 bpp RGB */ 177 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 178 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 179 180 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 181 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 182 183 /* 184 * Floating point 64bpp RGB 185 * IEEE 754-2008 binary16 half-precision float 186 * [15:0] sign:exponent:mantissa 1:5:10 187 */ 188 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 189 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 190 191 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 192 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 193 194 /* 195 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits 196 * of unused padding per component: 197 */ 198 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ 199 200 /* packed YCbCr */ 201 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 202 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 203 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 204 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 205 206 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 207 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 208 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ 209 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ 210 211 /* 212 * packed Y2xx indicate for each component, xx valid data occupy msb 213 * 16-xx padding occupy lsb 214 */ 215 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ 216 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ 217 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ 218 219 /* 220 * packed Y4xx indicate for each component, xx valid data occupy msb 221 * 16-xx padding occupy lsb except Y410 222 */ 223 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ 224 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 225 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ 226 227 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ 228 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 229 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ 230 231 /* 232 * packed YCbCr420 2x2 tiled formats 233 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 234 */ 235 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 236 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 237 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 238 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 239 240 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 241 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 242 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 243 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 244 245 /* 246 * 1-plane YUV 4:2:0 247 * In these formats, the component ordering is specified (Y, followed by U 248 * then V), but the exact Linear layout is undefined. 249 * These formats can only be used with a non-Linear modifier. 250 */ 251 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') 252 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') 253 254 /* 255 * 2 plane RGB + A 256 * index 0 = RGB plane, same format as the corresponding non _A8 format has 257 * index 1 = A plane, [7:0] A 258 */ 259 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 260 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 261 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 262 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 263 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 264 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 265 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 266 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 267 268 /* 269 * 2 plane YCbCr 270 * index 0 = Y plane, [7:0] Y 271 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 272 * or 273 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 274 */ 275 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 276 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 277 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 278 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 279 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 280 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 281 /* 282 * 2 plane YCbCr 283 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian 284 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian 285 */ 286 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ 287 288 /* 289 * 2 plane YCbCr MSB aligned 290 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 291 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 292 */ 293 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ 294 295 /* 296 * 2 plane YCbCr MSB aligned 297 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 298 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 299 */ 300 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ 301 302 /* 303 * 2 plane YCbCr MSB aligned 304 * index 0 = Y plane, [15:0] Y:x [12:4] little endian 305 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian 306 */ 307 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ 308 309 /* 310 * 2 plane YCbCr MSB aligned 311 * index 0 = Y plane, [15:0] Y little endian 312 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian 313 */ 314 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ 315 316 /* 3 plane non-subsampled (444) YCbCr 317 * 16 bits per component, but only 10 bits are used and 6 bits are padded 318 * index 0: Y plane, [15:0] Y:x [10:6] little endian 319 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian 320 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian 321 */ 322 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') 323 324 /* 3 plane non-subsampled (444) YCrCb 325 * 16 bits per component, but only 10 bits are used and 6 bits are padded 326 * index 0: Y plane, [15:0] Y:x [10:6] little endian 327 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian 328 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian 329 */ 330 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') 331 332 /* 333 * 3 plane YCbCr 334 * index 0: Y plane, [7:0] Y 335 * index 1: Cb plane, [7:0] Cb 336 * index 2: Cr plane, [7:0] Cr 337 * or 338 * index 1: Cr plane, [7:0] Cr 339 * index 2: Cb plane, [7:0] Cb 340 */ 341 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 342 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 343 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 344 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 345 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 346 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 347 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 348 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 349 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 350 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 351 352 353 /* 354 * Format Modifiers: 355 * 356 * Format modifiers describe, typically, a re-ordering or modification 357 * of the data in a plane of an FB. This can be used to express tiled/ 358 * swizzled formats, or compression, or a combination of the two. 359 * 360 * The upper 8 bits of the format modifier are a vendor-id as assigned 361 * below. The lower 56 bits are assigned as vendor sees fit. 362 */ 363 364 /* Vendor Ids: */ 365 #define DRM_FORMAT_MOD_VENDOR_NONE 0 366 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 367 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 368 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 369 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 370 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 371 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 372 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 373 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 374 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 375 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a 376 377 /* add more to the end as needed */ 378 379 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 380 381 #define fourcc_mod_get_vendor(modifier) \ 382 (((modifier) >> 56) & 0xff) 383 384 #define fourcc_mod_is_vendor(modifier, vendor) \ 385 (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) 386 387 #define fourcc_mod_code(vendor, val) \ 388 ((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 389 390 /* 391 * Format Modifier tokens: 392 * 393 * When adding a new token please document the layout with a code comment, 394 * similar to the fourcc codes above. drm_fourcc.h is considered the 395 * authoritative source for all of these. 396 * 397 * Generic modifier names: 398 * 399 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names 400 * for layouts which are common across multiple vendors. To preserve 401 * compatibility, in cases where a vendor-specific definition already exists and 402 * a generic name for it is desired, the common name is a purely symbolic alias 403 * and must use the same numerical value as the original definition. 404 * 405 * Note that generic names should only be used for modifiers which describe 406 * generic layouts (such as pixel re-ordering), which may have 407 * independently-developed support across multiple vendors. 408 * 409 * In future cases where a generic layout is identified before merging with a 410 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor 411 * 'NONE' could be considered. This should only be for obvious, exceptional 412 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only 413 * apply to a single vendor. 414 * 415 * Generic names should not be used for cases where multiple hardware vendors 416 * have implementations of the same standardised compression scheme (such as 417 * AFBC). In those cases, all implementations should use the same format 418 * modifier(s), reflecting the vendor of the standard. 419 */ 420 421 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE 422 423 /* 424 * Invalid Modifier 425 * 426 * This modifier can be used as a sentinel to terminate the format modifiers 427 * list, or to initialize a variable with an invalid modifier. It might also be 428 * used to report an error back to userspace for certain APIs. 429 */ 430 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 431 432 /* 433 * Linear Layout 434 * 435 * Just plain linear layout. Note that this is different from no specifying any 436 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 437 * which tells the driver to also take driver-internal information into account 438 * and so might actually result in a tiled framebuffer. 439 */ 440 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 441 442 /* 443 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead 444 * 445 * The "none" format modifier doesn't actually mean that the modifier is 446 * implicit, instead it means that the layout is linear. Whether modifiers are 447 * used is out-of-band information carried in an API-specific way (e.g. in a 448 * flag for drm_mode_fb_cmd2). 449 */ 450 #define DRM_FORMAT_MOD_NONE 0 451 452 /* Intel framebuffer modifiers */ 453 454 /* 455 * Intel X-tiling layout 456 * 457 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 458 * in row-major layout. Within the tile bytes are laid out row-major, with 459 * a platform-dependent stride. On top of that the memory can apply 460 * platform-depending swizzling of some higher address bits into bit6. 461 * 462 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 463 * On earlier platforms the is highly platforms specific and not useful for 464 * cross-driver sharing. It exists since on a given platform it does uniquely 465 * identify the layout in a simple way for i915-specific userspace, which 466 * facilitated conversion of userspace to modifiers. Additionally the exact 467 * format on some really old platforms is not known. 468 */ 469 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 470 471 /* 472 * Intel Y-tiling layout 473 * 474 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 475 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 476 * chunks column-major, with a platform-dependent height. On top of that the 477 * memory can apply platform-depending swizzling of some higher address bits 478 * into bit6. 479 * 480 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 481 * On earlier platforms the is highly platforms specific and not useful for 482 * cross-driver sharing. It exists since on a given platform it does uniquely 483 * identify the layout in a simple way for i915-specific userspace, which 484 * facilitated conversion of userspace to modifiers. Additionally the exact 485 * format on some really old platforms is not known. 486 */ 487 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 488 489 /* 490 * Intel Yf-tiling layout 491 * 492 * This is a tiled layout using 4Kb tiles in row-major layout. 493 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 494 * are arranged in four groups (two wide, two high) with column-major layout. 495 * Each group therefore consits out of four 256 byte units, which are also laid 496 * out as 2x2 column-major. 497 * 256 byte units are made out of four 64 byte blocks of pixels, producing 498 * either a square block or a 2:1 unit. 499 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 500 * in pixel depends on the pixel depth. 501 */ 502 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 503 504 /* 505 * Intel color control surface (CCS) for render compression 506 * 507 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 508 * The main surface will be plane index 0 and must be Y/Yf-tiled, 509 * the CCS will be plane index 1. 510 * 511 * Each CCS tile matches a 1024x512 pixel area of the main surface. 512 * To match certain aspects of the 3D hardware the CCS is 513 * considered to be made up of normal 128Bx32 Y tiles, Thus 514 * the CCS pitch must be specified in multiples of 128 bytes. 515 * 516 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 517 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 518 * But that fact is not relevant unless the memory is accessed 519 * directly. 520 */ 521 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 522 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 523 524 /* 525 * Intel color control surfaces (CCS) for Gen-12 render compression. 526 * 527 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 528 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 529 * main surface. In other words, 4 bits in CCS map to a main surface cache 530 * line pair. The main surface pitch is required to be a multiple of four 531 * Y-tile widths. 532 */ 533 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) 534 535 /* 536 * Intel color control surfaces (CCS) for Gen-12 media compression 537 * 538 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 539 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 540 * main surface. In other words, 4 bits in CCS map to a main surface cache 541 * line pair. The main surface pitch is required to be a multiple of four 542 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the 543 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 544 * planes 2 and 3 for the respective CCS. 545 */ 546 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) 547 548 /* 549 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render 550 * compression. 551 * 552 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear 553 * and at index 1. The clear color is stored at index 2, and the pitch should 554 * be ignored. The clear color structure is 256 bits. The first 128 bits 555 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 556 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 557 * the converted clear color of size 64 bits. The first 32 bits store the Lower 558 * Converted Clear Color value and the next 32 bits store the Higher Converted 559 * Clear Color value when applicable. The Converted Clear Color values are 560 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 561 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 562 * corresponds to an area of 4x1 tiles in the main surface. The main surface 563 * pitch is required to be a multiple of 4 tile widths. 564 */ 565 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) 566 567 /* 568 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 569 * 570 * Macroblocks are laid in a Z-shape, and each pixel data is following the 571 * standard NV12 style. 572 * As for NV12, an image is the result of two frame buffers: one for Y, 573 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 574 * Alignment requirements are (for each buffer): 575 * - multiple of 128 pixels for the width 576 * - multiple of 32 pixels for the height 577 * 578 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 579 */ 580 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 581 582 /* 583 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 584 * 585 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 586 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 587 * they correspond to their 16x16 luma block. 588 */ 589 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 590 591 /* 592 * Qualcomm Compressed Format 593 * 594 * Refers to a compressed variant of the base format that is compressed. 595 * Implementation may be platform and base-format specific. 596 * 597 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 598 * Pixel data pitch/stride is aligned with macrotile width. 599 * Pixel data height is aligned with macrotile height. 600 * Entire pixel data buffer is aligned with 4k(bytes). 601 */ 602 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 603 604 /* Vivante framebuffer modifiers */ 605 606 /* 607 * Vivante 4x4 tiling layout 608 * 609 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 610 * layout. 611 */ 612 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 613 614 /* 615 * Vivante 64x64 super-tiling layout 616 * 617 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 618 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 619 * major layout. 620 * 621 * For more information: see 622 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 623 */ 624 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 625 626 /* 627 * Vivante 4x4 tiling layout for dual-pipe 628 * 629 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 630 * different base address. Offsets from the base addresses are therefore halved 631 * compared to the non-split tiled layout. 632 */ 633 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 634 635 /* 636 * Vivante 64x64 super-tiling layout for dual-pipe 637 * 638 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 639 * starts at a different base address. Offsets from the base addresses are 640 * therefore halved compared to the non-split super-tiled layout. 641 */ 642 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 643 644 /* NVIDIA frame buffer modifiers */ 645 646 /* 647 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 648 * 649 * Pixels are arranged in simple tiles of 16 x 16 bytes. 650 */ 651 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 652 653 /* 654 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, 655 * and Tegra GPUs starting with Tegra K1. 656 * 657 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies 658 * based on the architecture generation. GOBs themselves are then arranged in 659 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power 660 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents 661 * a block depth or height of "4"). 662 * 663 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 664 * in full detail. 665 * 666 * Macro 667 * Bits Param Description 668 * ---- ----- ----------------------------------------------------------------- 669 * 670 * 3:0 h log2(height) of each block, in GOBs. Placed here for 671 * compatibility with the existing 672 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 673 * 674 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for 675 * compatibility with the existing 676 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 677 * 678 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block 679 * size). Must be zero. 680 * 681 * Note there is no log2(width) parameter. Some portions of the 682 * hardware support a block width of two gobs, but it is impractical 683 * to use due to lack of support elsewhere, and has no known 684 * benefits. 685 * 686 * 11:9 - Reserved (To support 2D-array textures with variable array stride 687 * in blocks, specified via log2(tile width in blocks)). Must be 688 * zero. 689 * 690 * 19:12 k Page Kind. This value directly maps to a field in the page 691 * tables of all GPUs >= NV50. It affects the exact layout of bits 692 * in memory and can be derived from the tuple 693 * 694 * (format, GPU model, compression type, samples per pixel) 695 * 696 * Where compression type is defined below. If GPU model were 697 * implied by the format modifier, format, or memory buffer, page 698 * kind would not need to be included in the modifier itself, but 699 * since the modifier should define the layout of the associated 700 * memory buffer independent from any device or other context, it 701 * must be included here. 702 * 703 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed 704 * starting with Fermi GPUs. Additionally, the mapping between page 705 * kind and bit layout has changed at various points. 706 * 707 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping 708 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping 709 * 2 = Gob Height 8, Turing+ Page Kind mapping 710 * 3 = Reserved for future use. 711 * 712 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 713 * bit remapping step that occurs at an even lower level than the 714 * page kind and block linear swizzles. This causes the layout of 715 * surfaces mapped in those SOC's GPUs to be incompatible with the 716 * equivalent mapping on other GPUs in the same system. 717 * 718 * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 719 * 1 = Desktop GPU and Tegra Xavier+ Layout 720 * 721 * 25:23 c Lossless Framebuffer Compression type. 722 * 723 * 0 = none 724 * 1 = ROP/3D, layout 1, exact compression format implied by Page 725 * Kind field 726 * 2 = ROP/3D, layout 2, exact compression format implied by Page 727 * Kind field 728 * 3 = CDE horizontal 729 * 4 = CDE vertical 730 * 5 = Reserved for future use 731 * 6 = Reserved for future use 732 * 7 = Reserved for future use 733 * 734 * 55:25 - Reserved for future use. Must be zero. 735 */ 736 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 737 fourcc_mod_code(NVIDIA, (0x10 | \ 738 ((h) & 0xf) | \ 739 (((k) & 0xff) << 12) | \ 740 (((g) & 0x3) << 20) | \ 741 (((s) & 0x1) << 22) | \ 742 (((c) & 0x7) << 23))) 743 744 /* To grandfather in prior block linear format modifiers to the above layout, 745 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable 746 * with block-linear layouts, is remapped within drivers to the value 0xfe, 747 * which corresponds to the "generic" kind used for simple single-sample 748 * uncompressed color formats on Fermi - Volta GPUs. 749 */ 750 static inline uint64_t 751 drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier) 752 { 753 if (!(modifier & 0x10) || (modifier & (0xff << 12))) 754 return modifier; 755 else 756 return modifier | (0xfe << 12); 757 } 758 759 /* 760 * 16Bx2 Block Linear layout, used by Tegra K1 and later 761 * 762 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 763 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 764 * 765 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 766 * 767 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 768 * Valid values are: 769 * 770 * 0 == ONE_GOB 771 * 1 == TWO_GOBS 772 * 2 == FOUR_GOBS 773 * 3 == EIGHT_GOBS 774 * 4 == SIXTEEN_GOBS 775 * 5 == THIRTYTWO_GOBS 776 * 777 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 778 * in full detail. 779 */ 780 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 781 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) 782 783 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 784 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) 785 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 786 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) 787 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 788 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) 789 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 790 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) 791 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 792 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) 793 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 794 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) 795 796 /* 797 * Some Broadcom modifiers take parameters, for example the number of 798 * vertical lines in the image. Reserve the lower 32 bits for modifier 799 * type, and the next 24 bits for parameters. Top 8 bits are the 800 * vendor code. 801 */ 802 #define __fourcc_mod_broadcom_param_shift 8 803 #define __fourcc_mod_broadcom_param_bits 48 804 #define fourcc_mod_broadcom_code(val, params) \ 805 fourcc_mod_code(BROADCOM, ((((uint64_t)params) << __fourcc_mod_broadcom_param_shift) | val)) 806 #define fourcc_mod_broadcom_param(m) \ 807 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 808 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 809 #define fourcc_mod_broadcom_mod(m) \ 810 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 811 __fourcc_mod_broadcom_param_shift)) 812 813 /* 814 * Broadcom VC4 "T" format 815 * 816 * This is the primary layout that the V3D GPU can texture from (it 817 * can't do linear). The T format has: 818 * 819 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 820 * pixels at 32 bit depth. 821 * 822 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 823 * 16x16 pixels). 824 * 825 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 826 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 827 * they're (TR, BR, BL, TL), where bottom left is start of memory. 828 * 829 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 830 * tiles) or right-to-left (odd rows of 4k tiles). 831 */ 832 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 833 834 /* 835 * Broadcom SAND format 836 * 837 * This is the native format that the H.264 codec block uses. For VC4 838 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 839 * 840 * The image can be considered to be split into columns, and the 841 * columns are placed consecutively into memory. The width of those 842 * columns can be either 32, 64, 128, or 256 pixels, but in practice 843 * only 128 pixel columns are used. 844 * 845 * The pitch between the start of each column is set to optimally 846 * switch between SDRAM banks. This is passed as the number of lines 847 * of column width in the modifier (we can't use the stride value due 848 * to various core checks that look at it , so you should set the 849 * stride to width*cpp). 850 * 851 * Note that the column height for this format modifier is the same 852 * for all of the planes, assuming that each column contains both Y 853 * and UV. Some SAND-using hardware stores UV in a separate tiled 854 * image from Y to reduce the column height, which is not supported 855 * with these modifiers. 856 */ 857 858 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 859 fourcc_mod_broadcom_code(2, v) 860 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 861 fourcc_mod_broadcom_code(3, v) 862 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 863 fourcc_mod_broadcom_code(4, v) 864 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 865 fourcc_mod_broadcom_code(5, v) 866 867 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 868 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 869 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 870 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 871 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 872 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 873 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 874 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 875 876 /* Broadcom UIF format 877 * 878 * This is the common format for the current Broadcom multimedia 879 * blocks, including V3D 3.x and newer, newer video codecs, and 880 * displays. 881 * 882 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 883 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 884 * stored in columns, with padding between the columns to ensure that 885 * moving from one column to the next doesn't hit the same SDRAM page 886 * bank. 887 * 888 * To calculate the padding, it is assumed that each hardware block 889 * and the software driving it knows the platform's SDRAM page size, 890 * number of banks, and XOR address, and that it's identical between 891 * all blocks using the format. This tiling modifier will use XOR as 892 * necessary to reduce the padding. If a hardware block can't do XOR, 893 * the assumption is that a no-XOR tiling modifier will be created. 894 */ 895 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 896 897 /* 898 * Arm Framebuffer Compression (AFBC) modifiers 899 * 900 * AFBC is a proprietary lossless image compression protocol and format. 901 * It provides fine-grained random access and minimizes the amount of data 902 * transferred between IP blocks. 903 * 904 * AFBC has several features which may be supported and/or used, which are 905 * represented using bits in the modifier. Not all combinations are valid, 906 * and different devices or use-cases may support different combinations. 907 * 908 * Further information on the use of AFBC modifiers can be found in 909 * Documentation/gpu/afbc.rst 910 */ 911 912 /* 913 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific 914 * modifiers) denote the category for modifiers. Currently we have three 915 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of 916 * sixteen different categories. 917 */ 918 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ 919 fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) 920 921 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 922 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 923 924 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ 925 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) 926 927 /* 928 * AFBC superblock size 929 * 930 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 931 * size (in pixels) must be aligned to a multiple of the superblock size. 932 * Four lowest significant bits(LSBs) are reserved for block size. 933 * 934 * Where one superblock size is specified, it applies to all planes of the 935 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, 936 * the first applies to the Luma plane and the second applies to the Chroma 937 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). 938 * Multiple superblock sizes are only valid for multi-plane YCbCr formats. 939 */ 940 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 941 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 942 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 943 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) 944 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) 945 946 /* 947 * AFBC lossless colorspace transform 948 * 949 * Indicates that the buffer makes use of the AFBC lossless colorspace 950 * transform. 951 */ 952 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 953 954 /* 955 * AFBC block-split 956 * 957 * Indicates that the payload of each superblock is split. The second 958 * half of the payload is positioned at a predefined offset from the start 959 * of the superblock payload. 960 */ 961 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 962 963 /* 964 * AFBC sparse layout 965 * 966 * This flag indicates that the payload of each superblock must be stored at a 967 * predefined position relative to the other superblocks in the same AFBC 968 * buffer. This order is the same order used by the header buffer. In this mode 969 * each superblock is given the same amount of space as an uncompressed 970 * superblock of the particular format would require, rounding up to the next 971 * multiple of 128 bytes in size. 972 */ 973 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 974 975 /* 976 * AFBC copy-block restrict 977 * 978 * Buffers with this flag must obey the copy-block restriction. The restriction 979 * is such that there are no copy-blocks referring across the border of 8x8 980 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 981 */ 982 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 983 984 /* 985 * AFBC tiled layout 986 * 987 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 988 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 989 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 990 * larger bpp formats. The order between the tiles is scan line. 991 * When the tiled layout is used, the buffer size (in pixels) must be aligned 992 * to the tile size. 993 */ 994 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 995 996 /* 997 * AFBC solid color blocks 998 * 999 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 1000 * can be reduced if a whole superblock is a single color. 1001 */ 1002 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 1003 1004 /* 1005 * AFBC double-buffer 1006 * 1007 * Indicates that the buffer is allocated in a layout safe for front-buffer 1008 * rendering. 1009 */ 1010 #define AFBC_FORMAT_MOD_DB (1ULL << 10) 1011 1012 /* 1013 * AFBC buffer content hints 1014 * 1015 * Indicates that the buffer includes per-superblock content hints. 1016 */ 1017 #define AFBC_FORMAT_MOD_BCH (1ULL << 11) 1018 1019 /* AFBC uncompressed storage mode 1020 * 1021 * Indicates that the buffer is using AFBC uncompressed storage mode. 1022 * In this mode all superblock payloads in the buffer use the uncompressed 1023 * storage mode, which is usually only used for data which cannot be compressed. 1024 * The buffer layout is the same as for AFBC buffers without USM set, this only 1025 * affects the storage mode of the individual superblocks. Note that even a 1026 * buffer without USM set may use uncompressed storage mode for some or all 1027 * superblocks, USM just guarantees it for all. 1028 */ 1029 #define AFBC_FORMAT_MOD_USM (1ULL << 12) 1030 1031 /* 1032 * Arm Fixed-Rate Compression (AFRC) modifiers 1033 * 1034 * AFRC is a proprietary fixed rate image compression protocol and format, 1035 * designed to provide guaranteed bandwidth and memory footprint 1036 * reductions in graphics and media use-cases. 1037 * 1038 * AFRC buffers consist of one or more planes, with the same components 1039 * and meaning as an uncompressed buffer using the same pixel format. 1040 * 1041 * Within each plane, the pixel/luma/chroma values are grouped into 1042 * "coding unit" blocks which are individually compressed to a 1043 * fixed size (in bytes). All coding units within a given plane of a buffer 1044 * store the same number of values, and have the same compressed size. 1045 * 1046 * The coding unit size is configurable, allowing different rates of compression. 1047 * 1048 * The start of each AFRC buffer plane must be aligned to an alignment granule which 1049 * depends on the coding unit size. 1050 * 1051 * Coding Unit Size Plane Alignment 1052 * ---------------- --------------- 1053 * 16 bytes 1024 bytes 1054 * 24 bytes 512 bytes 1055 * 32 bytes 2048 bytes 1056 * 1057 * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned 1058 * to a multiple of the paging tile dimensions. 1059 * The dimensions of each paging tile depend on whether the buffer is optimised for 1060 * scanline (SCAN layout) or rotated (ROT layout) access. 1061 * 1062 * Layout Paging Tile Width Paging Tile Height 1063 * ------ ----------------- ------------------ 1064 * SCAN 16 coding units 4 coding units 1065 * ROT 8 coding units 8 coding units 1066 * 1067 * The dimensions of each coding unit depend on the number of components 1068 * in the compressed plane and whether the buffer is optimised for 1069 * scanline (SCAN layout) or rotated (ROT layout) access. 1070 * 1071 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height 1072 * ----------------------------- --------- ----------------- ------------------ 1073 * 1 SCAN 16 samples 4 samples 1074 * Example: 16x4 luma samples in a 'Y' plane 1075 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1076 * ----------------------------- --------- ----------------- ------------------ 1077 * 1 ROT 8 samples 8 samples 1078 * Example: 8x8 luma samples in a 'Y' plane 1079 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1080 * ----------------------------- --------- ----------------- ------------------ 1081 * 2 DONT CARE 8 samples 4 samples 1082 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer 1083 * ----------------------------- --------- ----------------- ------------------ 1084 * 3 DONT CARE 4 samples 4 samples 1085 * Example: 4x4 pixels in an RGB buffer without alpha 1086 * ----------------------------- --------- ----------------- ------------------ 1087 * 4 DONT CARE 4 samples 4 samples 1088 * Example: 4x4 pixels in an RGB buffer with alpha 1089 */ 1090 1091 #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 1092 1093 #define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ 1094 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) 1095 1096 /* 1097 * AFRC coding unit size modifier. 1098 * 1099 * Indicates the number of bytes used to store each compressed coding unit for 1100 * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance 1101 * is the same for both Cb and Cr, which may be stored in separate planes. 1102 * 1103 * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store 1104 * each compressed coding unit in the first plane of the buffer. For RGBA buffers 1105 * this is the only plane, while for semi-planar and fully-planar YUV buffers, 1106 * this corresponds to the luma plane. 1107 * 1108 * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store 1109 * each compressed coding unit in the second and third planes in the buffer. 1110 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s). 1111 * 1112 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified 1113 * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero. 1114 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and 1115 * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified. 1116 */ 1117 #define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf 1118 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL) 1119 #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL) 1120 #define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL) 1121 1122 #define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size) 1123 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4) 1124 1125 /* 1126 * AFRC scanline memory layout. 1127 * 1128 * Indicates if the buffer uses the scanline-optimised layout 1129 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout. 1130 * The memory layout is the same for all planes. 1131 */ 1132 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) 1133 1134 /* 1135 * Arm 16x16 Block U-Interleaved modifier 1136 * 1137 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image 1138 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels 1139 * in the block are reordered. 1140 */ 1141 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ 1142 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) 1143 1144 /* 1145 * Allwinner tiled modifier 1146 * 1147 * This tiling mode is implemented by the VPU found on all Allwinner platforms, 1148 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 1149 * planes. 1150 * 1151 * With this tiling, the luminance samples are disposed in tiles representing 1152 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. 1153 * The pixel order in each tile is linear and the tiles are disposed linearly, 1154 * both in row-major order. 1155 */ 1156 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) 1157 1158 /* 1159 * Amlogic Video Framebuffer Compression modifiers 1160 * 1161 * Amlogic uses a proprietary lossless image compression protocol and format 1162 * for their hardware video codec accelerators, either video decoders or 1163 * video input encoders. 1164 * 1165 * It considerably reduces memory bandwidth while writing and reading 1166 * frames in memory. 1167 * 1168 * The underlying storage is considered to be 3 components, 8bit or 10-bit 1169 * per component YCbCr 420, single plane : 1170 * - DRM_FORMAT_YUV420_8BIT 1171 * - DRM_FORMAT_YUV420_10BIT 1172 * 1173 * The first 8 bits of the mode defines the layout, then the following 8 bits 1174 * defines the options changing the layout. 1175 * 1176 * Not all combinations are valid, and different SoCs may support different 1177 * combinations of layout and options. 1178 */ 1179 #define __fourcc_mod_amlogic_layout_mask 0xff 1180 #define __fourcc_mod_amlogic_options_shift 8 1181 #define __fourcc_mod_amlogic_options_mask 0xff 1182 1183 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ 1184 fourcc_mod_code(AMLOGIC, \ 1185 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ 1186 (((__options) & __fourcc_mod_amlogic_options_mask) \ 1187 << __fourcc_mod_amlogic_options_shift)) 1188 1189 /* Amlogic FBC Layouts */ 1190 1191 /* 1192 * Amlogic FBC Basic Layout 1193 * 1194 * The basic layout is composed of: 1195 * - a body content organized in 64x32 superblocks with 4096 bytes per 1196 * superblock in default mode. 1197 * - a 32 bytes per 128x64 header block 1198 * 1199 * This layout is transferrable between Amlogic SoCs supporting this modifier. 1200 */ 1201 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) 1202 1203 /* 1204 * Amlogic FBC Scatter Memory layout 1205 * 1206 * Indicates the header contains IOMMU references to the compressed 1207 * frames content to optimize memory access and layout. 1208 * 1209 * In this mode, only the header memory address is needed, thus the 1210 * content memory organization is tied to the current producer 1211 * execution and cannot be saved/dumped neither transferrable between 1212 * Amlogic SoCs supporting this modifier. 1213 * 1214 * Due to the nature of the layout, these buffers are not expected to 1215 * be accessible by the user-space clients, but only accessible by the 1216 * hardware producers and consumers. 1217 * 1218 * The user-space clients should expect a failure while trying to mmap 1219 * the DMA-BUF handle returned by the producer. 1220 */ 1221 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) 1222 1223 /* Amlogic FBC Layout Options Bit Mask */ 1224 1225 /* 1226 * Amlogic FBC Memory Saving mode 1227 * 1228 * Indicates the storage is packed when pixel size is multiple of word 1229 * boudaries, i.e. 8bit should be stored in this mode to save allocation 1230 * memory. 1231 * 1232 * This mode reduces body layout to 3072 bytes per 64x32 superblock with 1233 * the basic layout and 3200 bytes per 64x32 superblock combined with 1234 * the scatter layout. 1235 */ 1236 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) 1237 1238 /* 1239 * AMD modifiers 1240 * 1241 * Memory layout: 1242 * 1243 * without DCC: 1244 * - main surface 1245 * 1246 * with DCC & without DCC_RETILE: 1247 * - main surface in plane 0 1248 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) 1249 * 1250 * with DCC & DCC_RETILE: 1251 * - main surface in plane 0 1252 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) 1253 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) 1254 * 1255 * For multi-plane formats the above surfaces get merged into one plane for 1256 * each format plane, based on the required alignment only. 1257 * 1258 * Bits Parameter Notes 1259 * ----- ------------------------ --------------------------------------------- 1260 * 1261 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* 1262 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* 1263 * 13 DCC 1264 * 14 DCC_RETILE 1265 * 15 DCC_PIPE_ALIGN 1266 * 16 DCC_INDEPENDENT_64B 1267 * 17 DCC_INDEPENDENT_128B 1268 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* 1269 * 20 DCC_CONSTANT_ENCODE 1270 * 23:21 PIPE_XOR_BITS Only for some chips 1271 * 26:24 BANK_XOR_BITS Only for some chips 1272 * 29:27 PACKERS Only for some chips 1273 * 32:30 RB Only for some chips 1274 * 35:33 PIPE Only for some chips 1275 * 55:36 - Reserved for future use, must be zero 1276 */ 1277 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) 1278 1279 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) 1280 1281 /* Reserve 0 for GFX8 and older */ 1282 #define AMD_FMT_MOD_TILE_VER_GFX9 1 1283 #define AMD_FMT_MOD_TILE_VER_GFX10 2 1284 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 1285 1286 /* 1287 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical 1288 * version. 1289 */ 1290 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9 1291 1292 /* 1293 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has 1294 * GFX9 as canonical version. 1295 */ 1296 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 1297 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 1298 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 1299 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 1300 1301 #define AMD_FMT_MOD_DCC_BLOCK_64B 0 1302 #define AMD_FMT_MOD_DCC_BLOCK_128B 1 1303 #define AMD_FMT_MOD_DCC_BLOCK_256B 2 1304 1305 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 1306 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF 1307 #define AMD_FMT_MOD_TILE_SHIFT 8 1308 #define AMD_FMT_MOD_TILE_MASK 0x1F 1309 1310 /* Whether DCC compression is enabled. */ 1311 #define AMD_FMT_MOD_DCC_SHIFT 13 1312 #define AMD_FMT_MOD_DCC_MASK 0x1 1313 1314 /* 1315 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and 1316 * one which is not-aligned. 1317 */ 1318 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 1319 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 1320 1321 /* Only set if DCC_RETILE = false */ 1322 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 1323 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 1324 1325 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 1326 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 1327 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 1328 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 1329 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 1330 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 1331 1332 /* 1333 * DCC supports embedding some clear colors directly in the DCC surface. 1334 * However, on older GPUs the rendering HW ignores the embedded clear color 1335 * and prefers the driver provided color. This necessitates doing a fastclear 1336 * eliminate operation before a process transfers control. 1337 * 1338 * If this bit is set that means the fastclear eliminate is not needed for these 1339 * embeddable colors. 1340 */ 1341 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 1342 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 1343 1344 /* 1345 * The below fields are for accounting for per GPU differences. These are only 1346 * relevant for GFX9 and later and if the tile field is *_X/_T. 1347 * 1348 * PIPE_XOR_BITS = always needed 1349 * BANK_XOR_BITS = only for TILE_VER_GFX9 1350 * PACKERS = only for TILE_VER_GFX10_RBPLUS 1351 * RB = only for TILE_VER_GFX9 & DCC 1352 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) 1353 */ 1354 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 1355 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 1356 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 1357 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 1358 #define AMD_FMT_MOD_PACKERS_SHIFT 27 1359 #define AMD_FMT_MOD_PACKERS_MASK 0x7 1360 #define AMD_FMT_MOD_RB_SHIFT 30 1361 #define AMD_FMT_MOD_RB_MASK 0x7 1362 #define AMD_FMT_MOD_PIPE_SHIFT 33 1363 #define AMD_FMT_MOD_PIPE_MASK 0x7 1364 1365 #define AMD_FMT_MOD_SET(field, value) \ 1366 ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) 1367 #define AMD_FMT_MOD_GET(field, value) \ 1368 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) 1369 #define AMD_FMT_MOD_CLEAR(field) \ 1370 (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) 1371 1372 #if defined(__cplusplus) 1373 } 1374 #endif 1375 1376 #endif /* DRM_FOURCC_H */ 1377