1 /*
2  * Copyright 2011 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #ifndef DRM_FOURCC_H
25 #define DRM_FOURCC_H
26 
27 
28 #if defined(__cplusplus)
29 extern "C" {
30 #endif
31 
32 /**
33  * DOC: overview
34  *
35  * In the DRM subsystem, framebuffer pixel formats are described using the
36  * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
37  * fourcc code, a Format Modifier may optionally be provided, in order to
38  * further describe the buffer's format - for example tiling or compression.
39  *
40  * Format Modifiers
41  * ----------------
42  *
43  * Format modifiers are used in conjunction with a fourcc code, forming a
44  * unique fourcc:modifier pair. This format:modifier pair must fully define the
45  * format and data layout of the buffer, and should be the only way to describe
46  * that particular buffer.
47  *
48  * Having multiple fourcc:modifier pairs which describe the same layout should
49  * be avoided, as such aliases run the risk of different drivers exposing
50  * different names for the same data format, forcing userspace to understand
51  * that they are aliases.
52  *
53  * Format modifiers may change any property of the buffer, including the number
54  * of planes and/or the required allocation size. Format modifiers are
55  * vendor-namespaced, and as such the relationship between a fourcc code and a
56  * modifier is specific to the modifer being used. For example, some modifiers
57  * may preserve meaning - such as number of planes - from the fourcc code,
58  * whereas others may not.
59  *
60  * Modifiers must uniquely encode buffer layout. In other words, a buffer must
61  * match only a single modifier. A modifier must not be a subset of layouts of
62  * another modifier. For instance, it's incorrect to encode pitch alignment in
63  * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
64  * aligned modifier. That said, modifiers can have implicit minimal
65  * requirements.
66  *
67  * For modifiers where the combination of fourcc code and modifier can alias,
68  * a canonical pair needs to be defined and used by all drivers. Preferred
69  * combinations are also encouraged where all combinations might lead to
70  * confusion and unnecessarily reduced interoperability. An example for the
71  * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.
72  *
73  * There are two kinds of modifier users:
74  *
75  * - Kernel and user-space drivers: for drivers it's important that modifiers
76  *   don't alias, otherwise two drivers might support the same format but use
77  *   different aliases, preventing them from sharing buffers in an efficient
78  *   format.
79  * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
80  *   see modifiers as opaque tokens they can check for equality and intersect.
81  *   These users musn't need to know to reason about the modifier value
82  *   (i.e. they are not expected to extract information out of the modifier).
83  *
84  * Vendors should document their modifier usage in as much detail as
85  * possible, to ensure maximum compatibility across devices, drivers and
86  * applications.
87  *
88  * The authoritative list of format modifier codes is found in
89  * `include/uapi/drm/drm_fourcc.h`
90  */
91 
92 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \
93 				 ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
94 
95 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
96 
97 /* Reserve 0 for the invalid format specifier */
98 #define DRM_FORMAT_INVALID	0
99 
100 /* color index */
101 #define DRM_FORMAT_C1		fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
102 #define DRM_FORMAT_C2		fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
103 #define DRM_FORMAT_C4		fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
104 #define DRM_FORMAT_C8		fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
105 
106 /* 1 bpp Darkness (inverse relationship between channel value and brightness) */
107 #define DRM_FORMAT_D1		fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */
108 
109 /* 2 bpp Darkness (inverse relationship between channel value and brightness) */
110 #define DRM_FORMAT_D2		fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */
111 
112 /* 4 bpp Darkness (inverse relationship between channel value and brightness) */
113 #define DRM_FORMAT_D4		fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */
114 
115 /* 8 bpp Darkness (inverse relationship between channel value and brightness) */
116 #define DRM_FORMAT_D8		fourcc_code('D', '8', ' ', ' ') /* [7:0] D */
117 
118 /* 1 bpp Red (direct relationship between channel value and brightness) */
119 #define DRM_FORMAT_R1		fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */
120 
121 /* 2 bpp Red (direct relationship between channel value and brightness) */
122 #define DRM_FORMAT_R2		fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */
123 
124 /* 4 bpp Red (direct relationship between channel value and brightness) */
125 #define DRM_FORMAT_R4		fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */
126 
127 /* 8 bpp Red (direct relationship between channel value and brightness) */
128 #define DRM_FORMAT_R8		fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
129 
130 /* 10 bpp Red (direct relationship between channel value and brightness) */
131 #define DRM_FORMAT_R10		fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
132 
133 /* 12 bpp Red (direct relationship between channel value and brightness) */
134 #define DRM_FORMAT_R12		fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
135 
136 /* 16 bpp Red (direct relationship between channel value and brightness) */
137 #define DRM_FORMAT_R16		fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
138 
139 /* 16 bpp RG */
140 #define DRM_FORMAT_RG88		fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
141 #define DRM_FORMAT_GR88		fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
142 
143 /* 32 bpp RG */
144 #define DRM_FORMAT_RG1616	fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
145 #define DRM_FORMAT_GR1616	fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
146 
147 /* 8 bpp RGB */
148 #define DRM_FORMAT_RGB332	fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
149 #define DRM_FORMAT_BGR233	fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
150 
151 /* 16 bpp RGB */
152 #define DRM_FORMAT_XRGB4444	fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
153 #define DRM_FORMAT_XBGR4444	fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
154 #define DRM_FORMAT_RGBX4444	fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
155 #define DRM_FORMAT_BGRX4444	fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
156 
157 #define DRM_FORMAT_ARGB4444	fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
158 #define DRM_FORMAT_ABGR4444	fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
159 #define DRM_FORMAT_RGBA4444	fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
160 #define DRM_FORMAT_BGRA4444	fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
161 
162 #define DRM_FORMAT_XRGB1555	fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
163 #define DRM_FORMAT_XBGR1555	fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
164 #define DRM_FORMAT_RGBX5551	fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
165 #define DRM_FORMAT_BGRX5551	fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
166 
167 #define DRM_FORMAT_ARGB1555	fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
168 #define DRM_FORMAT_ABGR1555	fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
169 #define DRM_FORMAT_RGBA5551	fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
170 #define DRM_FORMAT_BGRA5551	fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
171 
172 #define DRM_FORMAT_RGB565	fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
173 #define DRM_FORMAT_BGR565	fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
174 
175 /* 24 bpp RGB */
176 #define DRM_FORMAT_RGB888	fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
177 #define DRM_FORMAT_BGR888	fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
178 
179 /* 32 bpp RGB */
180 #define DRM_FORMAT_XRGB8888	fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
181 #define DRM_FORMAT_XBGR8888	fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
182 #define DRM_FORMAT_RGBX8888	fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
183 #define DRM_FORMAT_BGRX8888	fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
184 
185 #define DRM_FORMAT_ARGB8888	fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
186 #define DRM_FORMAT_ABGR8888	fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
187 #define DRM_FORMAT_RGBA8888	fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
188 #define DRM_FORMAT_BGRA8888	fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
189 
190 #define DRM_FORMAT_XRGB2101010	fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
191 #define DRM_FORMAT_XBGR2101010	fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
192 #define DRM_FORMAT_RGBX1010102	fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
193 #define DRM_FORMAT_BGRX1010102	fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
194 
195 #define DRM_FORMAT_ARGB2101010	fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
196 #define DRM_FORMAT_ABGR2101010	fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
197 #define DRM_FORMAT_RGBA1010102	fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
198 #define DRM_FORMAT_BGRA1010102	fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
199 
200 /* 64 bpp RGB */
201 #define DRM_FORMAT_XRGB16161616	fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */
202 #define DRM_FORMAT_XBGR16161616	fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */
203 
204 #define DRM_FORMAT_ARGB16161616	fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */
205 #define DRM_FORMAT_ABGR16161616	fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */
206 
207 /*
208  * Floating point 64bpp RGB
209  * IEEE 754-2008 binary16 half-precision float
210  * [15:0] sign:exponent:mantissa 1:5:10
211  */
212 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
213 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
214 
215 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
216 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
217 
218 /*
219  * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
220  * of unused padding per component:
221  */
222 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
223 
224 /* packed YCbCr */
225 #define DRM_FORMAT_YUYV		fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
226 #define DRM_FORMAT_YVYU		fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
227 #define DRM_FORMAT_UYVY		fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
228 #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
229 
230 #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
231 #define DRM_FORMAT_AVUY8888	fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */
232 #define DRM_FORMAT_XYUV8888	fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
233 #define DRM_FORMAT_XVUY8888	fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */
234 #define DRM_FORMAT_VUY888	fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
235 #define DRM_FORMAT_VUY101010	fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
236 
237 /*
238  * packed Y2xx indicate for each component, xx valid data occupy msb
239  * 16-xx padding occupy lsb
240  */
241 #define DRM_FORMAT_Y210         fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
242 #define DRM_FORMAT_Y212         fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
243 #define DRM_FORMAT_Y216         fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
244 
245 /*
246  * packed Y4xx indicate for each component, xx valid data occupy msb
247  * 16-xx padding occupy lsb except Y410
248  */
249 #define DRM_FORMAT_Y410         fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
250 #define DRM_FORMAT_Y412         fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
251 #define DRM_FORMAT_Y416         fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
252 
253 #define DRM_FORMAT_XVYU2101010	fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
254 #define DRM_FORMAT_XVYU12_16161616	fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
255 #define DRM_FORMAT_XVYU16161616	fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
256 
257 /*
258  * packed YCbCr420 2x2 tiled formats
259  * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
260  */
261 /* [63:0]   A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0  1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
262 #define DRM_FORMAT_Y0L0		fourcc_code('Y', '0', 'L', '0')
263 /* [63:0]   X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0  1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
264 #define DRM_FORMAT_X0L0		fourcc_code('X', '0', 'L', '0')
265 
266 /* [63:0]   A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0  1:1:10:10:10:1:1:10:10:10 little endian */
267 #define DRM_FORMAT_Y0L2		fourcc_code('Y', '0', 'L', '2')
268 /* [63:0]   X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0  1:1:10:10:10:1:1:10:10:10 little endian */
269 #define DRM_FORMAT_X0L2		fourcc_code('X', '0', 'L', '2')
270 
271 /*
272  * 1-plane YUV 4:2:0
273  * In these formats, the component ordering is specified (Y, followed by U
274  * then V), but the exact Linear layout is undefined.
275  * These formats can only be used with a non-Linear modifier.
276  */
277 #define DRM_FORMAT_YUV420_8BIT	fourcc_code('Y', 'U', '0', '8')
278 #define DRM_FORMAT_YUV420_10BIT	fourcc_code('Y', 'U', '1', '0')
279 
280 /*
281  * 2 plane RGB + A
282  * index 0 = RGB plane, same format as the corresponding non _A8 format has
283  * index 1 = A plane, [7:0] A
284  */
285 #define DRM_FORMAT_XRGB8888_A8	fourcc_code('X', 'R', 'A', '8')
286 #define DRM_FORMAT_XBGR8888_A8	fourcc_code('X', 'B', 'A', '8')
287 #define DRM_FORMAT_RGBX8888_A8	fourcc_code('R', 'X', 'A', '8')
288 #define DRM_FORMAT_BGRX8888_A8	fourcc_code('B', 'X', 'A', '8')
289 #define DRM_FORMAT_RGB888_A8	fourcc_code('R', '8', 'A', '8')
290 #define DRM_FORMAT_BGR888_A8	fourcc_code('B', '8', 'A', '8')
291 #define DRM_FORMAT_RGB565_A8	fourcc_code('R', '5', 'A', '8')
292 #define DRM_FORMAT_BGR565_A8	fourcc_code('B', '5', 'A', '8')
293 
294 /*
295  * 2 plane YCbCr
296  * index 0 = Y plane, [7:0] Y
297  * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
298  * or
299  * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
300  */
301 #define DRM_FORMAT_NV12		fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
302 #define DRM_FORMAT_NV21		fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
303 #define DRM_FORMAT_NV16		fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
304 #define DRM_FORMAT_NV61		fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
305 #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
306 #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
307 /*
308  * 2 plane YCbCr
309  * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
310  * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
311  */
312 #define DRM_FORMAT_NV15		fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
313 
314 /*
315  * 2 plane YCbCr MSB aligned
316  * index 0 = Y plane, [15:0] Y:x [10:6] little endian
317  * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
318  */
319 #define DRM_FORMAT_P210		fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
320 
321 /*
322  * 2 plane YCbCr MSB aligned
323  * index 0 = Y plane, [15:0] Y:x [10:6] little endian
324  * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
325  */
326 #define DRM_FORMAT_P010		fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
327 
328 /*
329  * 2 plane YCbCr MSB aligned
330  * index 0 = Y plane, [15:0] Y:x [12:4] little endian
331  * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
332  */
333 #define DRM_FORMAT_P012		fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
334 
335 /*
336  * 2 plane YCbCr MSB aligned
337  * index 0 = Y plane, [15:0] Y little endian
338  * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
339  */
340 #define DRM_FORMAT_P016		fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
341 
342 /* 2 plane YCbCr420.
343  * 3 10 bit components and 2 padding bits packed into 4 bytes.
344  * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
345  * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
346  */
347 #define DRM_FORMAT_P030		fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
348 
349 /* 3 plane non-subsampled (444) YCbCr
350  * 16 bits per component, but only 10 bits are used and 6 bits are padded
351  * index 0: Y plane, [15:0] Y:x [10:6] little endian
352  * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
353  * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
354  */
355 #define DRM_FORMAT_Q410		fourcc_code('Q', '4', '1', '0')
356 
357 /* 3 plane non-subsampled (444) YCrCb
358  * 16 bits per component, but only 10 bits are used and 6 bits are padded
359  * index 0: Y plane, [15:0] Y:x [10:6] little endian
360  * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
361  * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
362  */
363 #define DRM_FORMAT_Q401		fourcc_code('Q', '4', '0', '1')
364 
365 /*
366  * 3 plane YCbCr
367  * index 0: Y plane, [7:0] Y
368  * index 1: Cb plane, [7:0] Cb
369  * index 2: Cr plane, [7:0] Cr
370  * or
371  * index 1: Cr plane, [7:0] Cr
372  * index 2: Cb plane, [7:0] Cb
373  */
374 #define DRM_FORMAT_YUV410	fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
375 #define DRM_FORMAT_YVU410	fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
376 #define DRM_FORMAT_YUV411	fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
377 #define DRM_FORMAT_YVU411	fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
378 #define DRM_FORMAT_YUV420	fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
379 #define DRM_FORMAT_YVU420	fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
380 #define DRM_FORMAT_YUV422	fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
381 #define DRM_FORMAT_YVU422	fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
382 #define DRM_FORMAT_YUV444	fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
383 #define DRM_FORMAT_YVU444	fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
384 
385 
386 /*
387  * Format Modifiers:
388  *
389  * Format modifiers describe, typically, a re-ordering or modification
390  * of the data in a plane of an FB.  This can be used to express tiled/
391  * swizzled formats, or compression, or a combination of the two.
392  *
393  * The upper 8 bits of the format modifier are a vendor-id as assigned
394  * below.  The lower 56 bits are assigned as vendor sees fit.
395  */
396 
397 /* Vendor Ids: */
398 #define DRM_FORMAT_MOD_VENDOR_NONE    0
399 #define DRM_FORMAT_MOD_VENDOR_INTEL   0x01
400 #define DRM_FORMAT_MOD_VENDOR_AMD     0x02
401 #define DRM_FORMAT_MOD_VENDOR_NVIDIA  0x03
402 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
403 #define DRM_FORMAT_MOD_VENDOR_QCOM    0x05
404 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
405 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
406 #define DRM_FORMAT_MOD_VENDOR_ARM     0x08
407 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
408 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
409 
410 /* add more to the end as needed */
411 
412 #define DRM_FORMAT_RESERVED	      ((1ULL << 56) - 1)
413 
414 #define fourcc_mod_get_vendor(modifier) \
415 	(((modifier) >> 56) & 0xff)
416 
417 #define fourcc_mod_is_vendor(modifier, vendor) \
418 	(fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor)
419 
420 #define fourcc_mod_code(vendor, val) \
421 	((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
422 
423 /*
424  * Format Modifier tokens:
425  *
426  * When adding a new token please document the layout with a code comment,
427  * similar to the fourcc codes above. drm_fourcc.h is considered the
428  * authoritative source for all of these.
429  *
430  * Generic modifier names:
431  *
432  * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
433  * for layouts which are common across multiple vendors. To preserve
434  * compatibility, in cases where a vendor-specific definition already exists and
435  * a generic name for it is desired, the common name is a purely symbolic alias
436  * and must use the same numerical value as the original definition.
437  *
438  * Note that generic names should only be used for modifiers which describe
439  * generic layouts (such as pixel re-ordering), which may have
440  * independently-developed support across multiple vendors.
441  *
442  * In future cases where a generic layout is identified before merging with a
443  * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
444  * 'NONE' could be considered. This should only be for obvious, exceptional
445  * cases to avoid polluting the 'GENERIC' namespace with modifiers which only
446  * apply to a single vendor.
447  *
448  * Generic names should not be used for cases where multiple hardware vendors
449  * have implementations of the same standardised compression scheme (such as
450  * AFBC). In those cases, all implementations should use the same format
451  * modifier(s), reflecting the vendor of the standard.
452  */
453 
454 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
455 
456 /*
457  * Invalid Modifier
458  *
459  * This modifier can be used as a sentinel to terminate the format modifiers
460  * list, or to initialize a variable with an invalid modifier. It might also be
461  * used to report an error back to userspace for certain APIs.
462  */
463 #define DRM_FORMAT_MOD_INVALID	fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
464 
465 /*
466  * Linear Layout
467  *
468  * Just plain linear layout. Note that this is different from no specifying any
469  * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
470  * which tells the driver to also take driver-internal information into account
471  * and so might actually result in a tiled framebuffer.
472  */
473 #define DRM_FORMAT_MOD_LINEAR	fourcc_mod_code(NONE, 0)
474 
475 /*
476  * Deprecated: use DRM_FORMAT_MOD_LINEAR instead
477  *
478  * The "none" format modifier doesn't actually mean that the modifier is
479  * implicit, instead it means that the layout is linear. Whether modifiers are
480  * used is out-of-band information carried in an API-specific way (e.g. in a
481  * flag for drm_mode_fb_cmd2).
482  */
483 #define DRM_FORMAT_MOD_NONE	0
484 
485 /* Intel framebuffer modifiers */
486 
487 /*
488  * Intel X-tiling layout
489  *
490  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
491  * in row-major layout. Within the tile bytes are laid out row-major, with
492  * a platform-dependent stride. On top of that the memory can apply
493  * platform-depending swizzling of some higher address bits into bit6.
494  *
495  * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
496  * On earlier platforms the is highly platforms specific and not useful for
497  * cross-driver sharing. It exists since on a given platform it does uniquely
498  * identify the layout in a simple way for i915-specific userspace, which
499  * facilitated conversion of userspace to modifiers. Additionally the exact
500  * format on some really old platforms is not known.
501  */
502 #define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 1)
503 
504 /*
505  * Intel Y-tiling layout
506  *
507  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
508  * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
509  * chunks column-major, with a platform-dependent height. On top of that the
510  * memory can apply platform-depending swizzling of some higher address bits
511  * into bit6.
512  *
513  * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
514  * On earlier platforms the is highly platforms specific and not useful for
515  * cross-driver sharing. It exists since on a given platform it does uniquely
516  * identify the layout in a simple way for i915-specific userspace, which
517  * facilitated conversion of userspace to modifiers. Additionally the exact
518  * format on some really old platforms is not known.
519  */
520 #define I915_FORMAT_MOD_Y_TILED	fourcc_mod_code(INTEL, 2)
521 
522 /*
523  * Intel Yf-tiling layout
524  *
525  * This is a tiled layout using 4Kb tiles in row-major layout.
526  * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
527  * are arranged in four groups (two wide, two high) with column-major layout.
528  * Each group therefore consits out of four 256 byte units, which are also laid
529  * out as 2x2 column-major.
530  * 256 byte units are made out of four 64 byte blocks of pixels, producing
531  * either a square block or a 2:1 unit.
532  * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
533  * in pixel depends on the pixel depth.
534  */
535 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
536 
537 /*
538  * Intel color control surface (CCS) for render compression
539  *
540  * The framebuffer format must be one of the 8:8:8:8 RGB formats.
541  * The main surface will be plane index 0 and must be Y/Yf-tiled,
542  * the CCS will be plane index 1.
543  *
544  * Each CCS tile matches a 1024x512 pixel area of the main surface.
545  * To match certain aspects of the 3D hardware the CCS is
546  * considered to be made up of normal 128Bx32 Y tiles, Thus
547  * the CCS pitch must be specified in multiples of 128 bytes.
548  *
549  * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
550  * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
551  * But that fact is not relevant unless the memory is accessed
552  * directly.
553  */
554 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
555 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
556 
557 /*
558  * Intel color control surfaces (CCS) for Gen-12 render compression.
559  *
560  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
561  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
562  * main surface. In other words, 4 bits in CCS map to a main surface cache
563  * line pair. The main surface pitch is required to be a multiple of four
564  * Y-tile widths.
565  */
566 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
567 
568 /*
569  * Intel color control surfaces (CCS) for Gen-12 media compression
570  *
571  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
572  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
573  * main surface. In other words, 4 bits in CCS map to a main surface cache
574  * line pair. The main surface pitch is required to be a multiple of four
575  * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
576  * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
577  * planes 2 and 3 for the respective CCS.
578  */
579 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
580 
581 /*
582  * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
583  * compression.
584  *
585  * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
586  * and at index 1. The clear color is stored at index 2, and the pitch should
587  * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits
588  * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
589  * by 32 bits. The raw clear color is consumed by the 3d engine and generates
590  * the converted clear color of size 64 bits. The first 32 bits store the Lower
591  * Converted Clear Color value and the next 32 bits store the Higher Converted
592  * Clear Color value when applicable. The Converted Clear Color values are
593  * consumed by the DE. The last 64 bits are used to store Color Discard Enable
594  * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
595  * corresponds to an area of 4x1 tiles in the main surface. The main surface
596  * pitch is required to be a multiple of 4 tile widths.
597  */
598 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
599 
600 /*
601  * Intel Tile 4 layout
602  *
603  * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
604  * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
605  * only differs from Tile Y at the 256B granularity in between. At this
606  * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
607  * of 64B x 8 rows.
608  */
609 #define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
610 
611 /*
612  * Intel color control surfaces (CCS) for DG2 render compression.
613  *
614  * The main surface is Tile 4 and at plane index 0. The CCS data is stored
615  * outside of the GEM object in a reserved memory area dedicated for the
616  * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
617  * main surface pitch is required to be a multiple of four Tile 4 widths.
618  */
619 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
620 
621 /*
622  * Intel color control surfaces (CCS) for DG2 media compression.
623  *
624  * The main surface is Tile 4 and at plane index 0. For semi-planar formats
625  * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
626  * 0 and 1, respectively. The CCS for all planes are stored outside of the
627  * GEM object in a reserved memory area dedicated for the storage of the
628  * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
629  * pitch is required to be a multiple of four Tile 4 widths.
630  */
631 #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
632 
633 /*
634  * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
635  *
636  * The main surface is Tile 4 and at plane index 0. The CCS data is stored
637  * outside of the GEM object in a reserved memory area dedicated for the
638  * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
639  * main surface pitch is required to be a multiple of four Tile 4 widths. The
640  * clear color is stored at plane index 1 and the pitch should be 64 bytes
641  * aligned. The format of the 256 bits of clear color data matches the one used
642  * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
643  * for details.
644  */
645 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
646 
647 /*
648  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
649  *
650  * Macroblocks are laid in a Z-shape, and each pixel data is following the
651  * standard NV12 style.
652  * As for NV12, an image is the result of two frame buffers: one for Y,
653  * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
654  * Alignment requirements are (for each buffer):
655  * - multiple of 128 pixels for the width
656  * - multiple of  32 pixels for the height
657  *
658  * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
659  */
660 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE	fourcc_mod_code(SAMSUNG, 1)
661 
662 /*
663  * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
664  *
665  * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
666  * layout. For YCbCr formats Cb/Cr components are taken in such a way that
667  * they correspond to their 16x16 luma block.
668  */
669 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE	fourcc_mod_code(SAMSUNG, 2)
670 
671 /*
672  * Qualcomm Compressed Format
673  *
674  * Refers to a compressed variant of the base format that is compressed.
675  * Implementation may be platform and base-format specific.
676  *
677  * Each macrotile consists of m x n (mostly 4 x 4) tiles.
678  * Pixel data pitch/stride is aligned with macrotile width.
679  * Pixel data height is aligned with macrotile height.
680  * Entire pixel data buffer is aligned with 4k(bytes).
681  */
682 #define DRM_FORMAT_MOD_QCOM_COMPRESSED	fourcc_mod_code(QCOM, 1)
683 
684 /*
685  * Qualcomm Tiled Format
686  *
687  * Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed.
688  * Implementation may be platform and base-format specific.
689  *
690  * Each macrotile consists of m x n (mostly 4 x 4) tiles.
691  * Pixel data pitch/stride is aligned with macrotile width.
692  * Pixel data height is aligned with macrotile height.
693  * Entire pixel data buffer is aligned with 4k(bytes).
694  */
695 #define DRM_FORMAT_MOD_QCOM_TILED3	fourcc_mod_code(QCOM, 3)
696 
697 /*
698  * Qualcomm Alternate Tiled Format
699  *
700  * Alternate tiled format typically only used within GMEM.
701  * Implementation may be platform and base-format specific.
702  */
703 #define DRM_FORMAT_MOD_QCOM_TILED2	fourcc_mod_code(QCOM, 2)
704 
705 
706 /* Vivante framebuffer modifiers */
707 
708 /*
709  * Vivante 4x4 tiling layout
710  *
711  * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
712  * layout.
713  */
714 #define DRM_FORMAT_MOD_VIVANTE_TILED		fourcc_mod_code(VIVANTE, 1)
715 
716 /*
717  * Vivante 64x64 super-tiling layout
718  *
719  * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
720  * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
721  * major layout.
722  *
723  * For more information: see
724  * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
725  */
726 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED	fourcc_mod_code(VIVANTE, 2)
727 
728 /*
729  * Vivante 4x4 tiling layout for dual-pipe
730  *
731  * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
732  * different base address. Offsets from the base addresses are therefore halved
733  * compared to the non-split tiled layout.
734  */
735 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED	fourcc_mod_code(VIVANTE, 3)
736 
737 /*
738  * Vivante 64x64 super-tiling layout for dual-pipe
739  *
740  * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
741  * starts at a different base address. Offsets from the base addresses are
742  * therefore halved compared to the non-split super-tiled layout.
743  */
744 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
745 
746 /* NVIDIA frame buffer modifiers */
747 
748 /*
749  * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
750  *
751  * Pixels are arranged in simple tiles of 16 x 16 bytes.
752  */
753 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
754 
755 /*
756  * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
757  * and Tegra GPUs starting with Tegra K1.
758  *
759  * Pixels are arranged in Groups of Bytes (GOBs).  GOB size and layout varies
760  * based on the architecture generation.  GOBs themselves are then arranged in
761  * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
762  * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
763  * a block depth or height of "4").
764  *
765  * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
766  * in full detail.
767  *
768  *       Macro
769  * Bits  Param Description
770  * ----  ----- -----------------------------------------------------------------
771  *
772  *  3:0  h     log2(height) of each block, in GOBs.  Placed here for
773  *             compatibility with the existing
774  *             DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
775  *
776  *  4:4  -     Must be 1, to indicate block-linear layout.  Necessary for
777  *             compatibility with the existing
778  *             DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
779  *
780  *  8:5  -     Reserved (To support 3D-surfaces with variable log2(depth) block
781  *             size).  Must be zero.
782  *
783  *             Note there is no log2(width) parameter.  Some portions of the
784  *             hardware support a block width of two gobs, but it is impractical
785  *             to use due to lack of support elsewhere, and has no known
786  *             benefits.
787  *
788  * 11:9  -     Reserved (To support 2D-array textures with variable array stride
789  *             in blocks, specified via log2(tile width in blocks)).  Must be
790  *             zero.
791  *
792  * 19:12 k     Page Kind.  This value directly maps to a field in the page
793  *             tables of all GPUs >= NV50.  It affects the exact layout of bits
794  *             in memory and can be derived from the tuple
795  *
796  *               (format, GPU model, compression type, samples per pixel)
797  *
798  *             Where compression type is defined below.  If GPU model were
799  *             implied by the format modifier, format, or memory buffer, page
800  *             kind would not need to be included in the modifier itself, but
801  *             since the modifier should define the layout of the associated
802  *             memory buffer independent from any device or other context, it
803  *             must be included here.
804  *
805  * 21:20 g     GOB Height and Page Kind Generation.  The height of a GOB changed
806  *             starting with Fermi GPUs.  Additionally, the mapping between page
807  *             kind and bit layout has changed at various points.
808  *
809  *               0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
810  *               1 = Gob Height 4, G80 - GT2XX Page Kind mapping
811  *               2 = Gob Height 8, Turing+ Page Kind mapping
812  *               3 = Reserved for future use.
813  *
814  * 22:22 s     Sector layout.  On Tegra GPUs prior to Xavier, there is a further
815  *             bit remapping step that occurs at an even lower level than the
816  *             page kind and block linear swizzles.  This causes the layout of
817  *             surfaces mapped in those SOC's GPUs to be incompatible with the
818  *             equivalent mapping on other GPUs in the same system.
819  *
820  *               0 = Tegra K1 - Tegra Parker/TX2 Layout.
821  *               1 = Desktop GPU and Tegra Xavier+ Layout
822  *
823  * 25:23 c     Lossless Framebuffer Compression type.
824  *
825  *               0 = none
826  *               1 = ROP/3D, layout 1, exact compression format implied by Page
827  *                   Kind field
828  *               2 = ROP/3D, layout 2, exact compression format implied by Page
829  *                   Kind field
830  *               3 = CDE horizontal
831  *               4 = CDE vertical
832  *               5 = Reserved for future use
833  *               6 = Reserved for future use
834  *               7 = Reserved for future use
835  *
836  * 55:25 -     Reserved for future use.  Must be zero.
837  */
838 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
839 	fourcc_mod_code(NVIDIA, (0x10 | \
840 				 ((h) & 0xf) | \
841 				 (((k) & 0xff) << 12) | \
842 				 (((g) & 0x3) << 20) | \
843 				 (((s) & 0x1) << 22) | \
844 				 (((c) & 0x7) << 23)))
845 
846 /* To grandfather in prior block linear format modifiers to the above layout,
847  * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
848  * with block-linear layouts, is remapped within drivers to the value 0xfe,
849  * which corresponds to the "generic" kind used for simple single-sample
850  * uncompressed color formats on Fermi - Volta GPUs.
851  */
852 static inline uint64_t
853 drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier)
854 {
855 	if (!(modifier & 0x10) || (modifier & (0xff << 12)))
856 		return modifier;
857 	else
858 		return modifier | (0xfe << 12);
859 }
860 
861 /*
862  * 16Bx2 Block Linear layout, used by Tegra K1 and later
863  *
864  * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
865  * vertically by a power of 2 (1 to 32 GOBs) to form a block.
866  *
867  * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
868  *
869  * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
870  * Valid values are:
871  *
872  * 0 == ONE_GOB
873  * 1 == TWO_GOBS
874  * 2 == FOUR_GOBS
875  * 3 == EIGHT_GOBS
876  * 4 == SIXTEEN_GOBS
877  * 5 == THIRTYTWO_GOBS
878  *
879  * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
880  * in full detail.
881  */
882 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
883 	DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
884 
885 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
886 	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
887 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
888 	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
889 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
890 	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
891 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
892 	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
893 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
894 	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
895 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
896 	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
897 
898 /*
899  * Some Broadcom modifiers take parameters, for example the number of
900  * vertical lines in the image. Reserve the lower 32 bits for modifier
901  * type, and the next 24 bits for parameters. Top 8 bits are the
902  * vendor code.
903  */
904 #define __fourcc_mod_broadcom_param_shift 8
905 #define __fourcc_mod_broadcom_param_bits 48
906 #define fourcc_mod_broadcom_code(val, params) \
907 	fourcc_mod_code(BROADCOM, ((((uint64_t)params) << __fourcc_mod_broadcom_param_shift) | val))
908 #define fourcc_mod_broadcom_param(m) \
909 	((int)(((m) >> __fourcc_mod_broadcom_param_shift) &	\
910 	       ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
911 #define fourcc_mod_broadcom_mod(m) \
912 	((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) <<	\
913 		 __fourcc_mod_broadcom_param_shift))
914 
915 /*
916  * Broadcom VC4 "T" format
917  *
918  * This is the primary layout that the V3D GPU can texture from (it
919  * can't do linear).  The T format has:
920  *
921  * - 64b utiles of pixels in a raster-order grid according to cpp.  It's 4x4
922  *   pixels at 32 bit depth.
923  *
924  * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
925  *   16x16 pixels).
926  *
927  * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels).  On
928  *   even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
929  *   they're (TR, BR, BL, TL), where bottom left is start of memory.
930  *
931  * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
932  *   tiles) or right-to-left (odd rows of 4k tiles).
933  */
934 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
935 
936 /*
937  * Broadcom SAND format
938  *
939  * This is the native format that the H.264 codec block uses.  For VC4
940  * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
941  *
942  * The image can be considered to be split into columns, and the
943  * columns are placed consecutively into memory.  The width of those
944  * columns can be either 32, 64, 128, or 256 pixels, but in practice
945  * only 128 pixel columns are used.
946  *
947  * The pitch between the start of each column is set to optimally
948  * switch between SDRAM banks. This is passed as the number of lines
949  * of column width in the modifier (we can't use the stride value due
950  * to various core checks that look at it , so you should set the
951  * stride to width*cpp).
952  *
953  * Note that the column height for this format modifier is the same
954  * for all of the planes, assuming that each column contains both Y
955  * and UV.  Some SAND-using hardware stores UV in a separate tiled
956  * image from Y to reduce the column height, which is not supported
957  * with these modifiers.
958  *
959  * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
960  * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
961  * wide, but as this is a 10 bpp format that translates to 96 pixels.
962  */
963 
964 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
965 	fourcc_mod_broadcom_code(2, v)
966 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
967 	fourcc_mod_broadcom_code(3, v)
968 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
969 	fourcc_mod_broadcom_code(4, v)
970 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
971 	fourcc_mod_broadcom_code(5, v)
972 
973 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
974 	DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
975 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
976 	DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
977 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
978 	DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
979 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
980 	DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
981 
982 /* Broadcom UIF format
983  *
984  * This is the common format for the current Broadcom multimedia
985  * blocks, including V3D 3.x and newer, newer video codecs, and
986  * displays.
987  *
988  * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
989  * and macroblocks (4x4 UIF blocks).  Those 4x4 UIF block groups are
990  * stored in columns, with padding between the columns to ensure that
991  * moving from one column to the next doesn't hit the same SDRAM page
992  * bank.
993  *
994  * To calculate the padding, it is assumed that each hardware block
995  * and the software driving it knows the platform's SDRAM page size,
996  * number of banks, and XOR address, and that it's identical between
997  * all blocks using the format.  This tiling modifier will use XOR as
998  * necessary to reduce the padding.  If a hardware block can't do XOR,
999  * the assumption is that a no-XOR tiling modifier will be created.
1000  */
1001 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
1002 
1003 /*
1004  * Arm Framebuffer Compression (AFBC) modifiers
1005  *
1006  * AFBC is a proprietary lossless image compression protocol and format.
1007  * It provides fine-grained random access and minimizes the amount of data
1008  * transferred between IP blocks.
1009  *
1010  * AFBC has several features which may be supported and/or used, which are
1011  * represented using bits in the modifier. Not all combinations are valid,
1012  * and different devices or use-cases may support different combinations.
1013  *
1014  * Further information on the use of AFBC modifiers can be found in
1015  * Documentation/gpu/afbc.rst
1016  */
1017 
1018 /*
1019  * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
1020  * modifiers) denote the category for modifiers. Currently we have three
1021  * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
1022  * sixteen different categories.
1023  */
1024 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
1025 	fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
1026 
1027 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
1028 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
1029 
1030 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
1031 	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
1032 
1033 /*
1034  * AFBC superblock size
1035  *
1036  * Indicates the superblock size(s) used for the AFBC buffer. The buffer
1037  * size (in pixels) must be aligned to a multiple of the superblock size.
1038  * Four lowest significant bits(LSBs) are reserved for block size.
1039  *
1040  * Where one superblock size is specified, it applies to all planes of the
1041  * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
1042  * the first applies to the Luma plane and the second applies to the Chroma
1043  * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
1044  * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
1045  */
1046 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK      0xf
1047 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16     (1ULL)
1048 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8      (2ULL)
1049 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4      (3ULL)
1050 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
1051 
1052 /*
1053  * AFBC lossless colorspace transform
1054  *
1055  * Indicates that the buffer makes use of the AFBC lossless colorspace
1056  * transform.
1057  */
1058 #define AFBC_FORMAT_MOD_YTR     (1ULL <<  4)
1059 
1060 /*
1061  * AFBC block-split
1062  *
1063  * Indicates that the payload of each superblock is split. The second
1064  * half of the payload is positioned at a predefined offset from the start
1065  * of the superblock payload.
1066  */
1067 #define AFBC_FORMAT_MOD_SPLIT   (1ULL <<  5)
1068 
1069 /*
1070  * AFBC sparse layout
1071  *
1072  * This flag indicates that the payload of each superblock must be stored at a
1073  * predefined position relative to the other superblocks in the same AFBC
1074  * buffer. This order is the same order used by the header buffer. In this mode
1075  * each superblock is given the same amount of space as an uncompressed
1076  * superblock of the particular format would require, rounding up to the next
1077  * multiple of 128 bytes in size.
1078  */
1079 #define AFBC_FORMAT_MOD_SPARSE  (1ULL <<  6)
1080 
1081 /*
1082  * AFBC copy-block restrict
1083  *
1084  * Buffers with this flag must obey the copy-block restriction. The restriction
1085  * is such that there are no copy-blocks referring across the border of 8x8
1086  * blocks. For the subsampled data the 8x8 limitation is also subsampled.
1087  */
1088 #define AFBC_FORMAT_MOD_CBR     (1ULL <<  7)
1089 
1090 /*
1091  * AFBC tiled layout
1092  *
1093  * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
1094  * superblocks inside a tile are stored together in memory. 8x8 tiles are used
1095  * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
1096  * larger bpp formats. The order between the tiles is scan line.
1097  * When the tiled layout is used, the buffer size (in pixels) must be aligned
1098  * to the tile size.
1099  */
1100 #define AFBC_FORMAT_MOD_TILED   (1ULL <<  8)
1101 
1102 /*
1103  * AFBC solid color blocks
1104  *
1105  * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1106  * can be reduced if a whole superblock is a single color.
1107  */
1108 #define AFBC_FORMAT_MOD_SC      (1ULL <<  9)
1109 
1110 /*
1111  * AFBC double-buffer
1112  *
1113  * Indicates that the buffer is allocated in a layout safe for front-buffer
1114  * rendering.
1115  */
1116 #define AFBC_FORMAT_MOD_DB      (1ULL << 10)
1117 
1118 /*
1119  * AFBC buffer content hints
1120  *
1121  * Indicates that the buffer includes per-superblock content hints.
1122  */
1123 #define AFBC_FORMAT_MOD_BCH     (1ULL << 11)
1124 
1125 /* AFBC uncompressed storage mode
1126  *
1127  * Indicates that the buffer is using AFBC uncompressed storage mode.
1128  * In this mode all superblock payloads in the buffer use the uncompressed
1129  * storage mode, which is usually only used for data which cannot be compressed.
1130  * The buffer layout is the same as for AFBC buffers without USM set, this only
1131  * affects the storage mode of the individual superblocks. Note that even a
1132  * buffer without USM set may use uncompressed storage mode for some or all
1133  * superblocks, USM just guarantees it for all.
1134  */
1135 #define AFBC_FORMAT_MOD_USM	(1ULL << 12)
1136 
1137 /*
1138  * Arm Fixed-Rate Compression (AFRC) modifiers
1139  *
1140  * AFRC is a proprietary fixed rate image compression protocol and format,
1141  * designed to provide guaranteed bandwidth and memory footprint
1142  * reductions in graphics and media use-cases.
1143  *
1144  * AFRC buffers consist of one or more planes, with the same components
1145  * and meaning as an uncompressed buffer using the same pixel format.
1146  *
1147  * Within each plane, the pixel/luma/chroma values are grouped into
1148  * "coding unit" blocks which are individually compressed to a
1149  * fixed size (in bytes). All coding units within a given plane of a buffer
1150  * store the same number of values, and have the same compressed size.
1151  *
1152  * The coding unit size is configurable, allowing different rates of compression.
1153  *
1154  * The start of each AFRC buffer plane must be aligned to an alignment granule which
1155  * depends on the coding unit size.
1156  *
1157  * Coding Unit Size   Plane Alignment
1158  * ----------------   ---------------
1159  * 16 bytes           1024 bytes
1160  * 24 bytes           512  bytes
1161  * 32 bytes           2048 bytes
1162  *
1163  * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned
1164  * to a multiple of the paging tile dimensions.
1165  * The dimensions of each paging tile depend on whether the buffer is optimised for
1166  * scanline (SCAN layout) or rotated (ROT layout) access.
1167  *
1168  * Layout   Paging Tile Width   Paging Tile Height
1169  * ------   -----------------   ------------------
1170  * SCAN     16 coding units     4 coding units
1171  * ROT      8  coding units     8 coding units
1172  *
1173  * The dimensions of each coding unit depend on the number of components
1174  * in the compressed plane and whether the buffer is optimised for
1175  * scanline (SCAN layout) or rotated (ROT layout) access.
1176  *
1177  * Number of Components in Plane   Layout      Coding Unit Width   Coding Unit Height
1178  * -----------------------------   ---------   -----------------   ------------------
1179  * 1                               SCAN        16 samples          4 samples
1180  * Example: 16x4 luma samples in a 'Y' plane
1181  *          16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1182  * -----------------------------   ---------   -----------------   ------------------
1183  * 1                               ROT         8 samples           8 samples
1184  * Example: 8x8 luma samples in a 'Y' plane
1185  *          8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1186  * -----------------------------   ---------   -----------------   ------------------
1187  * 2                               DONT CARE   8 samples           4 samples
1188  * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1189  * -----------------------------   ---------   -----------------   ------------------
1190  * 3                               DONT CARE   4 samples           4 samples
1191  * Example: 4x4 pixels in an RGB buffer without alpha
1192  * -----------------------------   ---------   -----------------   ------------------
1193  * 4                               DONT CARE   4 samples           4 samples
1194  * Example: 4x4 pixels in an RGB buffer with alpha
1195  */
1196 
1197 #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02
1198 
1199 #define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \
1200 	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode)
1201 
1202 /*
1203  * AFRC coding unit size modifier.
1204  *
1205  * Indicates the number of bytes used to store each compressed coding unit for
1206  * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance
1207  * is the same for both Cb and Cr, which may be stored in separate planes.
1208  *
1209  * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store
1210  * each compressed coding unit in the first plane of the buffer. For RGBA buffers
1211  * this is the only plane, while for semi-planar and fully-planar YUV buffers,
1212  * this corresponds to the luma plane.
1213  *
1214  * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store
1215  * each compressed coding unit in the second and third planes in the buffer.
1216  * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1217  *
1218  * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1219  * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero.
1220  * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1221  * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified.
1222  */
1223 #define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf
1224 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)
1225 #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL)
1226 #define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL)
1227 
1228 #define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size)
1229 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)
1230 
1231 /*
1232  * AFRC scanline memory layout.
1233  *
1234  * Indicates if the buffer uses the scanline-optimised layout
1235  * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1236  * The memory layout is the same for all planes.
1237  */
1238 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
1239 
1240 /*
1241  * Arm 16x16 Block U-Interleaved modifier
1242  *
1243  * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
1244  * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
1245  * in the block are reordered.
1246  */
1247 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
1248 	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
1249 
1250 /*
1251  * Allwinner tiled modifier
1252  *
1253  * This tiling mode is implemented by the VPU found on all Allwinner platforms,
1254  * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1255  * planes.
1256  *
1257  * With this tiling, the luminance samples are disposed in tiles representing
1258  * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
1259  * The pixel order in each tile is linear and the tiles are disposed linearly,
1260  * both in row-major order.
1261  */
1262 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
1263 
1264 /*
1265  * Amlogic Video Framebuffer Compression modifiers
1266  *
1267  * Amlogic uses a proprietary lossless image compression protocol and format
1268  * for their hardware video codec accelerators, either video decoders or
1269  * video input encoders.
1270  *
1271  * It considerably reduces memory bandwidth while writing and reading
1272  * frames in memory.
1273  *
1274  * The underlying storage is considered to be 3 components, 8bit or 10-bit
1275  * per component YCbCr 420, single plane :
1276  * - DRM_FORMAT_YUV420_8BIT
1277  * - DRM_FORMAT_YUV420_10BIT
1278  *
1279  * The first 8 bits of the mode defines the layout, then the following 8 bits
1280  * defines the options changing the layout.
1281  *
1282  * Not all combinations are valid, and different SoCs may support different
1283  * combinations of layout and options.
1284  */
1285 #define __fourcc_mod_amlogic_layout_mask 0xff
1286 #define __fourcc_mod_amlogic_options_shift 8
1287 #define __fourcc_mod_amlogic_options_mask 0xff
1288 
1289 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
1290 	fourcc_mod_code(AMLOGIC, \
1291 			((__layout) & __fourcc_mod_amlogic_layout_mask) | \
1292 			(((__options) & __fourcc_mod_amlogic_options_mask) \
1293 			 << __fourcc_mod_amlogic_options_shift))
1294 
1295 /* Amlogic FBC Layouts */
1296 
1297 /*
1298  * Amlogic FBC Basic Layout
1299  *
1300  * The basic layout is composed of:
1301  * - a body content organized in 64x32 superblocks with 4096 bytes per
1302  *   superblock in default mode.
1303  * - a 32 bytes per 128x64 header block
1304  *
1305  * This layout is transferrable between Amlogic SoCs supporting this modifier.
1306  */
1307 #define AMLOGIC_FBC_LAYOUT_BASIC		(1ULL)
1308 
1309 /*
1310  * Amlogic FBC Scatter Memory layout
1311  *
1312  * Indicates the header contains IOMMU references to the compressed
1313  * frames content to optimize memory access and layout.
1314  *
1315  * In this mode, only the header memory address is needed, thus the
1316  * content memory organization is tied to the current producer
1317  * execution and cannot be saved/dumped neither transferrable between
1318  * Amlogic SoCs supporting this modifier.
1319  *
1320  * Due to the nature of the layout, these buffers are not expected to
1321  * be accessible by the user-space clients, but only accessible by the
1322  * hardware producers and consumers.
1323  *
1324  * The user-space clients should expect a failure while trying to mmap
1325  * the DMA-BUF handle returned by the producer.
1326  */
1327 #define AMLOGIC_FBC_LAYOUT_SCATTER		(2ULL)
1328 
1329 /* Amlogic FBC Layout Options Bit Mask */
1330 
1331 /*
1332  * Amlogic FBC Memory Saving mode
1333  *
1334  * Indicates the storage is packed when pixel size is multiple of word
1335  * boudaries, i.e. 8bit should be stored in this mode to save allocation
1336  * memory.
1337  *
1338  * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1339  * the basic layout and 3200 bytes per 64x32 superblock combined with
1340  * the scatter layout.
1341  */
1342 #define AMLOGIC_FBC_OPTION_MEM_SAVING		(1ULL << 0)
1343 
1344 /*
1345  * AMD modifiers
1346  *
1347  * Memory layout:
1348  *
1349  * without DCC:
1350  *   - main surface
1351  *
1352  * with DCC & without DCC_RETILE:
1353  *   - main surface in plane 0
1354  *   - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1355  *
1356  * with DCC & DCC_RETILE:
1357  *   - main surface in plane 0
1358  *   - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1359  *   - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1360  *
1361  * For multi-plane formats the above surfaces get merged into one plane for
1362  * each format plane, based on the required alignment only.
1363  *
1364  * Bits  Parameter                Notes
1365  * ----- ------------------------ ---------------------------------------------
1366  *
1367  *   7:0 TILE_VERSION             Values are AMD_FMT_MOD_TILE_VER_*
1368  *  12:8 TILE                     Values are AMD_FMT_MOD_TILE_<version>_*
1369  *    13 DCC
1370  *    14 DCC_RETILE
1371  *    15 DCC_PIPE_ALIGN
1372  *    16 DCC_INDEPENDENT_64B
1373  *    17 DCC_INDEPENDENT_128B
1374  * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
1375  *    20 DCC_CONSTANT_ENCODE
1376  * 23:21 PIPE_XOR_BITS            Only for some chips
1377  * 26:24 BANK_XOR_BITS            Only for some chips
1378  * 29:27 PACKERS                  Only for some chips
1379  * 32:30 RB                       Only for some chips
1380  * 35:33 PIPE                     Only for some chips
1381  * 55:36 -                        Reserved for future use, must be zero
1382  */
1383 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
1384 
1385 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
1386 
1387 /* Reserve 0 for GFX8 and older */
1388 #define AMD_FMT_MOD_TILE_VER_GFX9 1
1389 #define AMD_FMT_MOD_TILE_VER_GFX10 2
1390 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
1391 #define AMD_FMT_MOD_TILE_VER_GFX11 4
1392 
1393 /*
1394  * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
1395  * version.
1396  */
1397 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9
1398 
1399 /*
1400  * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1401  * GFX9 as canonical version.
1402  */
1403 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10
1404 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
1405 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
1406 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
1407 #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31
1408 
1409 #define AMD_FMT_MOD_DCC_BLOCK_64B 0
1410 #define AMD_FMT_MOD_DCC_BLOCK_128B 1
1411 #define AMD_FMT_MOD_DCC_BLOCK_256B 2
1412 
1413 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
1414 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
1415 #define AMD_FMT_MOD_TILE_SHIFT 8
1416 #define AMD_FMT_MOD_TILE_MASK 0x1F
1417 
1418 /* Whether DCC compression is enabled. */
1419 #define AMD_FMT_MOD_DCC_SHIFT 13
1420 #define AMD_FMT_MOD_DCC_MASK 0x1
1421 
1422 /*
1423  * Whether to include two DCC surfaces, one which is rb & pipe aligned, and
1424  * one which is not-aligned.
1425  */
1426 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
1427 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
1428 
1429 /* Only set if DCC_RETILE = false */
1430 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
1431 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
1432 
1433 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
1434 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
1435 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
1436 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
1437 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
1438 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
1439 
1440 /*
1441  * DCC supports embedding some clear colors directly in the DCC surface.
1442  * However, on older GPUs the rendering HW ignores the embedded clear color
1443  * and prefers the driver provided color. This necessitates doing a fastclear
1444  * eliminate operation before a process transfers control.
1445  *
1446  * If this bit is set that means the fastclear eliminate is not needed for these
1447  * embeddable colors.
1448  */
1449 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
1450 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
1451 
1452 /*
1453  * The below fields are for accounting for per GPU differences. These are only
1454  * relevant for GFX9 and later and if the tile field is *_X/_T.
1455  *
1456  * PIPE_XOR_BITS = always needed
1457  * BANK_XOR_BITS = only for TILE_VER_GFX9
1458  * PACKERS = only for TILE_VER_GFX10_RBPLUS
1459  * RB = only for TILE_VER_GFX9 & DCC
1460  * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
1461  */
1462 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
1463 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
1464 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
1465 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
1466 #define AMD_FMT_MOD_PACKERS_SHIFT 27
1467 #define AMD_FMT_MOD_PACKERS_MASK 0x7
1468 #define AMD_FMT_MOD_RB_SHIFT 30
1469 #define AMD_FMT_MOD_RB_MASK 0x7
1470 #define AMD_FMT_MOD_PIPE_SHIFT 33
1471 #define AMD_FMT_MOD_PIPE_MASK 0x7
1472 
1473 #define AMD_FMT_MOD_SET(field, value) \
1474 	((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
1475 #define AMD_FMT_MOD_GET(field, value) \
1476 	(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
1477 #define AMD_FMT_MOD_CLEAR(field) \
1478 	(~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
1479 
1480 #if defined(__cplusplus)
1481 }
1482 #endif
1483 
1484 #endif /* DRM_FOURCC_H */
1485