1 /*
2  * Virtio GPU Device
3  *
4  * Copyright Red Hat, Inc. 2013-2014
5  *
6  * Authors:
7  *     Dave Airlie <airlied@redhat.com>
8  *     Gerd Hoffmann <kraxel@redhat.com>
9  *
10  * This header is BSD licensed so anyone can use the definitions
11  * to implement compatible drivers/servers:
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  * 1. Redistributions of source code must retain the above copyright
17  *    notice, this list of conditions and the following disclaimer.
18  * 2. Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the distribution.
21  * 3. Neither the name of IBM nor the names of its contributors
22  *    may be used to endorse or promote products derived from this software
23  *    without specific prior written permission.
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
27  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR
28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
31  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
34  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35  * SUCH DAMAGE.
36  */
37 
38 #ifndef VIRTIO_GPU_HW_H
39 #define VIRTIO_GPU_HW_H
40 
41 #include "standard-headers/linux/types.h"
42 
43 /*
44  * VIRTIO_GPU_CMD_CTX_*
45  * VIRTIO_GPU_CMD_*_3D
46  */
47 #define VIRTIO_GPU_F_VIRGL               0
48 
49 /*
50  * VIRTIO_GPU_CMD_GET_EDID
51  */
52 #define VIRTIO_GPU_F_EDID                1
53 /*
54  * VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID
55  */
56 #define VIRTIO_GPU_F_RESOURCE_UUID       2
57 
58 /*
59  * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB
60  */
61 #define VIRTIO_GPU_F_RESOURCE_BLOB       3
62 /*
63  * VIRTIO_GPU_CMD_CREATE_CONTEXT with
64  * context_init and multiple timelines
65  */
66 #define VIRTIO_GPU_F_CONTEXT_INIT        4
67 
68 enum virtio_gpu_ctrl_type {
69 	VIRTIO_GPU_UNDEFINED = 0,
70 
71 	/* 2d commands */
72 	VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
73 	VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
74 	VIRTIO_GPU_CMD_RESOURCE_UNREF,
75 	VIRTIO_GPU_CMD_SET_SCANOUT,
76 	VIRTIO_GPU_CMD_RESOURCE_FLUSH,
77 	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
78 	VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
79 	VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
80 	VIRTIO_GPU_CMD_GET_CAPSET_INFO,
81 	VIRTIO_GPU_CMD_GET_CAPSET,
82 	VIRTIO_GPU_CMD_GET_EDID,
83 	VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,
84 	VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB,
85 	VIRTIO_GPU_CMD_SET_SCANOUT_BLOB,
86 
87 	/* 3d commands */
88 	VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
89 	VIRTIO_GPU_CMD_CTX_DESTROY,
90 	VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
91 	VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
92 	VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
93 	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
94 	VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
95 	VIRTIO_GPU_CMD_SUBMIT_3D,
96 	VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB,
97 	VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB,
98 
99 	/* cursor commands */
100 	VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
101 	VIRTIO_GPU_CMD_MOVE_CURSOR,
102 
103 	/* success responses */
104 	VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
105 	VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
106 	VIRTIO_GPU_RESP_OK_CAPSET_INFO,
107 	VIRTIO_GPU_RESP_OK_CAPSET,
108 	VIRTIO_GPU_RESP_OK_EDID,
109 	VIRTIO_GPU_RESP_OK_RESOURCE_UUID,
110 	VIRTIO_GPU_RESP_OK_MAP_INFO,
111 
112 	/* error responses */
113 	VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
114 	VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
115 	VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
116 	VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
117 	VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
118 	VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
119 };
120 
121 enum virtio_gpu_shm_id {
122 	VIRTIO_GPU_SHM_ID_UNDEFINED = 0,
123 	/*
124 	 * VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB
125 	 * VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB
126 	 */
127 	VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1
128 };
129 
130 #define VIRTIO_GPU_FLAG_FENCE         (1 << 0)
131 /*
132  * If the following flag is set, then ring_idx contains the index
133  * of the command ring that needs to used when creating the fence
134  */
135 #define VIRTIO_GPU_FLAG_INFO_RING_IDX (1 << 1)
136 
137 struct virtio_gpu_ctrl_hdr {
138 	uint32_t type;
139 	uint32_t flags;
140 	uint64_t fence_id;
141 	uint32_t ctx_id;
142 	uint8_t ring_idx;
143 	uint8_t padding[3];
144 };
145 
146 /* data passed in the cursor vq */
147 
148 struct virtio_gpu_cursor_pos {
149 	uint32_t scanout_id;
150 	uint32_t x;
151 	uint32_t y;
152 	uint32_t padding;
153 };
154 
155 /* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
156 struct virtio_gpu_update_cursor {
157 	struct virtio_gpu_ctrl_hdr hdr;
158 	struct virtio_gpu_cursor_pos pos;  /* update & move */
159 	uint32_t resource_id;           /* update only */
160 	uint32_t hot_x;                 /* update only */
161 	uint32_t hot_y;                 /* update only */
162 	uint32_t padding;
163 };
164 
165 /* data passed in the control vq, 2d related */
166 
167 struct virtio_gpu_rect {
168 	uint32_t x;
169 	uint32_t y;
170 	uint32_t width;
171 	uint32_t height;
172 };
173 
174 /* VIRTIO_GPU_CMD_RESOURCE_UNREF */
175 struct virtio_gpu_resource_unref {
176 	struct virtio_gpu_ctrl_hdr hdr;
177 	uint32_t resource_id;
178 	uint32_t padding;
179 };
180 
181 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
182 struct virtio_gpu_resource_create_2d {
183 	struct virtio_gpu_ctrl_hdr hdr;
184 	uint32_t resource_id;
185 	uint32_t format;
186 	uint32_t width;
187 	uint32_t height;
188 };
189 
190 /* VIRTIO_GPU_CMD_SET_SCANOUT */
191 struct virtio_gpu_set_scanout {
192 	struct virtio_gpu_ctrl_hdr hdr;
193 	struct virtio_gpu_rect r;
194 	uint32_t scanout_id;
195 	uint32_t resource_id;
196 };
197 
198 /* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
199 struct virtio_gpu_resource_flush {
200 	struct virtio_gpu_ctrl_hdr hdr;
201 	struct virtio_gpu_rect r;
202 	uint32_t resource_id;
203 	uint32_t padding;
204 };
205 
206 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
207 struct virtio_gpu_transfer_to_host_2d {
208 	struct virtio_gpu_ctrl_hdr hdr;
209 	struct virtio_gpu_rect r;
210 	uint64_t offset;
211 	uint32_t resource_id;
212 	uint32_t padding;
213 };
214 
215 struct virtio_gpu_mem_entry {
216 	uint64_t addr;
217 	uint32_t length;
218 	uint32_t padding;
219 };
220 
221 /* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
222 struct virtio_gpu_resource_attach_backing {
223 	struct virtio_gpu_ctrl_hdr hdr;
224 	uint32_t resource_id;
225 	uint32_t nr_entries;
226 };
227 
228 /* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
229 struct virtio_gpu_resource_detach_backing {
230 	struct virtio_gpu_ctrl_hdr hdr;
231 	uint32_t resource_id;
232 	uint32_t padding;
233 };
234 
235 /* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
236 #define VIRTIO_GPU_MAX_SCANOUTS 16
237 struct virtio_gpu_resp_display_info {
238 	struct virtio_gpu_ctrl_hdr hdr;
239 	struct virtio_gpu_display_one {
240 		struct virtio_gpu_rect r;
241 		uint32_t enabled;
242 		uint32_t flags;
243 	} pmodes[VIRTIO_GPU_MAX_SCANOUTS];
244 };
245 
246 /* data passed in the control vq, 3d related */
247 
248 struct virtio_gpu_box {
249 	uint32_t x, y, z;
250 	uint32_t w, h, d;
251 };
252 
253 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
254 struct virtio_gpu_transfer_host_3d {
255 	struct virtio_gpu_ctrl_hdr hdr;
256 	struct virtio_gpu_box box;
257 	uint64_t offset;
258 	uint32_t resource_id;
259 	uint32_t level;
260 	uint32_t stride;
261 	uint32_t layer_stride;
262 };
263 
264 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
265 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
266 struct virtio_gpu_resource_create_3d {
267 	struct virtio_gpu_ctrl_hdr hdr;
268 	uint32_t resource_id;
269 	uint32_t target;
270 	uint32_t format;
271 	uint32_t bind;
272 	uint32_t width;
273 	uint32_t height;
274 	uint32_t depth;
275 	uint32_t array_size;
276 	uint32_t last_level;
277 	uint32_t nr_samples;
278 	uint32_t flags;
279 	uint32_t padding;
280 };
281 
282 /* VIRTIO_GPU_CMD_CTX_CREATE */
283 #define VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK 0x000000ff
284 struct virtio_gpu_ctx_create {
285 	struct virtio_gpu_ctrl_hdr hdr;
286 	uint32_t nlen;
287 	uint32_t context_init;
288 	char debug_name[64];
289 };
290 
291 /* VIRTIO_GPU_CMD_CTX_DESTROY */
292 struct virtio_gpu_ctx_destroy {
293 	struct virtio_gpu_ctrl_hdr hdr;
294 };
295 
296 /* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
297 struct virtio_gpu_ctx_resource {
298 	struct virtio_gpu_ctrl_hdr hdr;
299 	uint32_t resource_id;
300 	uint32_t padding;
301 };
302 
303 /* VIRTIO_GPU_CMD_SUBMIT_3D */
304 struct virtio_gpu_cmd_submit {
305 	struct virtio_gpu_ctrl_hdr hdr;
306 	uint32_t size;
307 	uint32_t padding;
308 };
309 
310 #define VIRTIO_GPU_CAPSET_VIRGL 1
311 #define VIRTIO_GPU_CAPSET_VIRGL2 2
312 /* 3 is reserved for gfxstream */
313 #define VIRTIO_GPU_CAPSET_VENUS 4
314 
315 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
316 struct virtio_gpu_get_capset_info {
317 	struct virtio_gpu_ctrl_hdr hdr;
318 	uint32_t capset_index;
319 	uint32_t padding;
320 };
321 
322 /* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
323 struct virtio_gpu_resp_capset_info {
324 	struct virtio_gpu_ctrl_hdr hdr;
325 	uint32_t capset_id;
326 	uint32_t capset_max_version;
327 	uint32_t capset_max_size;
328 	uint32_t padding;
329 };
330 
331 /* VIRTIO_GPU_CMD_GET_CAPSET */
332 struct virtio_gpu_get_capset {
333 	struct virtio_gpu_ctrl_hdr hdr;
334 	uint32_t capset_id;
335 	uint32_t capset_version;
336 };
337 
338 /* VIRTIO_GPU_RESP_OK_CAPSET */
339 struct virtio_gpu_resp_capset {
340 	struct virtio_gpu_ctrl_hdr hdr;
341 	uint8_t capset_data[];
342 };
343 
344 /* VIRTIO_GPU_CMD_GET_EDID */
345 struct virtio_gpu_cmd_get_edid {
346 	struct virtio_gpu_ctrl_hdr hdr;
347 	uint32_t scanout;
348 	uint32_t padding;
349 };
350 
351 /* VIRTIO_GPU_RESP_OK_EDID */
352 struct virtio_gpu_resp_edid {
353 	struct virtio_gpu_ctrl_hdr hdr;
354 	uint32_t size;
355 	uint32_t padding;
356 	uint8_t edid[1024];
357 };
358 
359 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
360 
361 struct virtio_gpu_config {
362 	uint32_t events_read;
363 	uint32_t events_clear;
364 	uint32_t num_scanouts;
365 	uint32_t num_capsets;
366 };
367 
368 /* simple formats for fbcon/X use */
369 enum virtio_gpu_formats {
370 	VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM  = 1,
371 	VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM  = 2,
372 	VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM  = 3,
373 	VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM  = 4,
374 
375 	VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM  = 67,
376 	VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM  = 68,
377 
378 	VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM  = 121,
379 	VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM  = 134,
380 };
381 
382 /* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */
383 struct virtio_gpu_resource_assign_uuid {
384 	struct virtio_gpu_ctrl_hdr hdr;
385 	uint32_t resource_id;
386 	uint32_t padding;
387 };
388 
389 /* VIRTIO_GPU_RESP_OK_RESOURCE_UUID */
390 struct virtio_gpu_resp_resource_uuid {
391 	struct virtio_gpu_ctrl_hdr hdr;
392 	uint8_t uuid[16];
393 };
394 
395 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */
396 struct virtio_gpu_resource_create_blob {
397 	struct virtio_gpu_ctrl_hdr hdr;
398 	uint32_t resource_id;
399 #define VIRTIO_GPU_BLOB_MEM_GUEST             0x0001
400 #define VIRTIO_GPU_BLOB_MEM_HOST3D            0x0002
401 #define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST      0x0003
402 
403 #define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE     0x0001
404 #define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE    0x0002
405 #define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
406 	/* zero is invalid blob mem */
407 	uint32_t blob_mem;
408 	uint32_t blob_flags;
409 	uint32_t nr_entries;
410 	uint64_t blob_id;
411 	uint64_t size;
412 	/*
413 	 * sizeof(nr_entries * virtio_gpu_mem_entry) bytes follow
414 	 */
415 };
416 
417 /* VIRTIO_GPU_CMD_SET_SCANOUT_BLOB */
418 struct virtio_gpu_set_scanout_blob {
419 	struct virtio_gpu_ctrl_hdr hdr;
420 	struct virtio_gpu_rect r;
421 	uint32_t scanout_id;
422 	uint32_t resource_id;
423 	uint32_t width;
424 	uint32_t height;
425 	uint32_t format;
426 	uint32_t padding;
427 	uint32_t strides[4];
428 	uint32_t offsets[4];
429 };
430 
431 /* VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB */
432 struct virtio_gpu_resource_map_blob {
433 	struct virtio_gpu_ctrl_hdr hdr;
434 	uint32_t resource_id;
435 	uint32_t padding;
436 	uint64_t offset;
437 };
438 
439 /* VIRTIO_GPU_RESP_OK_MAP_INFO */
440 #define VIRTIO_GPU_MAP_CACHE_MASK     0x0f
441 #define VIRTIO_GPU_MAP_CACHE_NONE     0x00
442 #define VIRTIO_GPU_MAP_CACHE_CACHED   0x01
443 #define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02
444 #define VIRTIO_GPU_MAP_CACHE_WC       0x03
445 struct virtio_gpu_resp_map_info {
446 	struct virtio_gpu_ctrl_hdr hdr;
447 	uint32_t map_info;
448 	uint32_t padding;
449 };
450 
451 /* VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB */
452 struct virtio_gpu_resource_unmap_blob {
453 	struct virtio_gpu_ctrl_hdr hdr;
454 	uint32_t resource_id;
455 	uint32_t padding;
456 };
457 
458 #endif
459