1*d3582cfdSPhilippe Mathieu-Daudé /* 2*d3582cfdSPhilippe Mathieu-Daudé * Generic vector operation descriptor 3*d3582cfdSPhilippe Mathieu-Daudé * 4*d3582cfdSPhilippe Mathieu-Daudé * Copyright (c) 2018 Linaro 5*d3582cfdSPhilippe Mathieu-Daudé * 6*d3582cfdSPhilippe Mathieu-Daudé * This library is free software; you can redistribute it and/or 7*d3582cfdSPhilippe Mathieu-Daudé * modify it under the terms of the GNU Lesser General Public 8*d3582cfdSPhilippe Mathieu-Daudé * License as published by the Free Software Foundation; either 9*d3582cfdSPhilippe Mathieu-Daudé * version 2.1 of the License, or (at your option) any later version. 10*d3582cfdSPhilippe Mathieu-Daudé * 11*d3582cfdSPhilippe Mathieu-Daudé * This library is distributed in the hope that it will be useful, 12*d3582cfdSPhilippe Mathieu-Daudé * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*d3582cfdSPhilippe Mathieu-Daudé * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14*d3582cfdSPhilippe Mathieu-Daudé * Lesser General Public License for more details. 15*d3582cfdSPhilippe Mathieu-Daudé * 16*d3582cfdSPhilippe Mathieu-Daudé * You should have received a copy of the GNU Lesser General Public 17*d3582cfdSPhilippe Mathieu-Daudé * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18*d3582cfdSPhilippe Mathieu-Daudé */ 19*d3582cfdSPhilippe Mathieu-Daudé 20*d3582cfdSPhilippe Mathieu-Daudé #ifndef TCG_TCG_GVEC_DESC_H 21*d3582cfdSPhilippe Mathieu-Daudé #define TCG_TCG_GVEC_DESC_H 22*d3582cfdSPhilippe Mathieu-Daudé 23*d3582cfdSPhilippe Mathieu-Daudé /* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */ 24*d3582cfdSPhilippe Mathieu-Daudé #define SIMD_OPRSZ_SHIFT 0 25*d3582cfdSPhilippe Mathieu-Daudé #define SIMD_OPRSZ_BITS 5 26*d3582cfdSPhilippe Mathieu-Daudé 27*d3582cfdSPhilippe Mathieu-Daudé #define SIMD_MAXSZ_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS) 28*d3582cfdSPhilippe Mathieu-Daudé #define SIMD_MAXSZ_BITS 5 29*d3582cfdSPhilippe Mathieu-Daudé 30*d3582cfdSPhilippe Mathieu-Daudé #define SIMD_DATA_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS) 31*d3582cfdSPhilippe Mathieu-Daudé #define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT) 32*d3582cfdSPhilippe Mathieu-Daudé 33*d3582cfdSPhilippe Mathieu-Daudé /* Create a descriptor from components. */ 34*d3582cfdSPhilippe Mathieu-Daudé uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data); 35*d3582cfdSPhilippe Mathieu-Daudé 36*d3582cfdSPhilippe Mathieu-Daudé /* Extract the operation size from a descriptor. */ 37*d3582cfdSPhilippe Mathieu-Daudé static inline intptr_t simd_oprsz(uint32_t desc) 38*d3582cfdSPhilippe Mathieu-Daudé { 39*d3582cfdSPhilippe Mathieu-Daudé return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8; 40*d3582cfdSPhilippe Mathieu-Daudé } 41*d3582cfdSPhilippe Mathieu-Daudé 42*d3582cfdSPhilippe Mathieu-Daudé /* Extract the max vector size from a descriptor. */ 43*d3582cfdSPhilippe Mathieu-Daudé static inline intptr_t simd_maxsz(uint32_t desc) 44*d3582cfdSPhilippe Mathieu-Daudé { 45*d3582cfdSPhilippe Mathieu-Daudé return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8; 46*d3582cfdSPhilippe Mathieu-Daudé } 47*d3582cfdSPhilippe Mathieu-Daudé 48*d3582cfdSPhilippe Mathieu-Daudé /* Extract the operation-specific data from a descriptor. */ 49*d3582cfdSPhilippe Mathieu-Daudé static inline int32_t simd_data(uint32_t desc) 50*d3582cfdSPhilippe Mathieu-Daudé { 51*d3582cfdSPhilippe Mathieu-Daudé return sextract32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS); 52*d3582cfdSPhilippe Mathieu-Daudé } 53*d3582cfdSPhilippe Mathieu-Daudé 54*d3582cfdSPhilippe Mathieu-Daudé #endif 55