1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_TCG_OP_H 26 #define TCG_TCG_OP_H 27 28 #include "tcg/tcg.h" 29 #include "exec/helper-proto.h" 30 #include "exec/helper-gen.h" 31 32 /* Basic output routines. Not for general consumption. */ 33 34 void tcg_gen_op1(TCGOpcode, TCGArg); 35 void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg); 36 void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg); 37 void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg); 38 void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); 39 void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); 40 41 void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg); 42 void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg); 43 void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg); 44 45 static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) 46 { 47 tcg_gen_op1(opc, tcgv_i32_arg(a1)); 48 } 49 50 static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) 51 { 52 tcg_gen_op1(opc, tcgv_i64_arg(a1)); 53 } 54 55 static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) 56 { 57 tcg_gen_op1(opc, a1); 58 } 59 60 static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) 61 { 62 tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2)); 63 } 64 65 static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) 66 { 67 tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2)); 68 } 69 70 static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) 71 { 72 tcg_gen_op2(opc, tcgv_i32_arg(a1), a2); 73 } 74 75 static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) 76 { 77 tcg_gen_op2(opc, tcgv_i64_arg(a1), a2); 78 } 79 80 static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) 81 { 82 tcg_gen_op2(opc, a1, a2); 83 } 84 85 static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, 86 TCGv_i32 a2, TCGv_i32 a3) 87 { 88 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3)); 89 } 90 91 static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, 92 TCGv_i64 a2, TCGv_i64 a3) 93 { 94 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3)); 95 } 96 97 static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, 98 TCGv_i32 a2, TCGArg a3) 99 { 100 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3); 101 } 102 103 static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, 104 TCGv_i64 a2, TCGArg a3) 105 { 106 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3); 107 } 108 109 static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, 110 TCGv_ptr base, TCGArg offset) 111 { 112 tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset); 113 } 114 115 static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, 116 TCGv_ptr base, TCGArg offset) 117 { 118 tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset); 119 } 120 121 static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 122 TCGv_i32 a3, TCGv_i32 a4) 123 { 124 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 125 tcgv_i32_arg(a3), tcgv_i32_arg(a4)); 126 } 127 128 static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 129 TCGv_i64 a3, TCGv_i64 a4) 130 { 131 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 132 tcgv_i64_arg(a3), tcgv_i64_arg(a4)); 133 } 134 135 static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 136 TCGv_i32 a3, TCGArg a4) 137 { 138 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 139 tcgv_i32_arg(a3), a4); 140 } 141 142 static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 143 TCGv_i64 a3, TCGArg a4) 144 { 145 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 146 tcgv_i64_arg(a3), a4); 147 } 148 149 static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 150 TCGArg a3, TCGArg a4) 151 { 152 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4); 153 } 154 155 static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 156 TCGArg a3, TCGArg a4) 157 { 158 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4); 159 } 160 161 static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 162 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) 163 { 164 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 165 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5)); 166 } 167 168 static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 169 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) 170 { 171 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 172 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5)); 173 } 174 175 static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 176 TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) 177 { 178 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 179 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5); 180 } 181 182 static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 183 TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) 184 { 185 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 186 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5); 187 } 188 189 static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 190 TCGv_i32 a3, TCGArg a4, TCGArg a5) 191 { 192 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 193 tcgv_i32_arg(a3), a4, a5); 194 } 195 196 static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 197 TCGv_i64 a3, TCGArg a4, TCGArg a5) 198 { 199 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 200 tcgv_i64_arg(a3), a4, a5); 201 } 202 203 static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 204 TCGv_i32 a3, TCGv_i32 a4, 205 TCGv_i32 a5, TCGv_i32 a6) 206 { 207 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 208 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), 209 tcgv_i32_arg(a6)); 210 } 211 212 static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 213 TCGv_i64 a3, TCGv_i64 a4, 214 TCGv_i64 a5, TCGv_i64 a6) 215 { 216 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 217 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), 218 tcgv_i64_arg(a6)); 219 } 220 221 static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 222 TCGv_i32 a3, TCGv_i32 a4, 223 TCGv_i32 a5, TCGArg a6) 224 { 225 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 226 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6); 227 } 228 229 static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 230 TCGv_i64 a3, TCGv_i64 a4, 231 TCGv_i64 a5, TCGArg a6) 232 { 233 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 234 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); 235 } 236 237 static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 238 TCGv_i32 a3, TCGv_i32 a4, 239 TCGArg a5, TCGArg a6) 240 { 241 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 242 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); 243 } 244 245 static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 246 TCGv_i64 a3, TCGv_i64 a4, 247 TCGArg a5, TCGArg a6) 248 { 249 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 250 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6); 251 } 252 253 254 /* Generic ops. */ 255 256 static inline void gen_set_label(TCGLabel *l) 257 { 258 l->present = 1; 259 tcg_gen_op1(INDEX_op_set_label, label_arg(l)); 260 } 261 262 void tcg_gen_br(TCGLabel *l); 263 void tcg_gen_mb(TCGBar); 264 265 /* Helper calls. */ 266 267 /* 32 bit ops */ 268 269 void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg); 270 void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 271 void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); 272 void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 273 void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 274 void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 275 void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 276 void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 277 void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 278 void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 279 void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 280 void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 281 void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 282 void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 283 void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 284 void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 285 void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 286 void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 287 void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 288 void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 289 void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 290 void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 291 void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); 292 void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); 293 void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); 294 void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2); 295 void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 296 void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 297 void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 298 void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 299 void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, 300 unsigned int ofs, unsigned int len); 301 void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, 302 unsigned int ofs, unsigned int len); 303 void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, 304 unsigned int ofs, unsigned int len); 305 void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, 306 unsigned int ofs, unsigned int len); 307 void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, 308 unsigned int ofs); 309 void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *); 310 void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *); 311 void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, 312 TCGv_i32 arg1, TCGv_i32 arg2); 313 void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, 314 TCGv_i32 arg1, int32_t arg2); 315 void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, 316 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); 317 void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, 318 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); 319 void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, 320 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); 321 void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); 322 void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); 323 void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); 324 void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg); 325 void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg); 326 void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); 327 void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); 328 void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); 329 void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); 330 void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); 331 void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); 332 void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); 333 void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); 334 void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); 335 void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); 336 337 /* Replicate a value of size @vece from @in to all the lanes in @out */ 338 void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); 339 340 static inline void tcg_gen_discard_i32(TCGv_i32 arg) 341 { 342 tcg_gen_op1_i32(INDEX_op_discard, arg); 343 } 344 345 static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) 346 { 347 if (ret != arg) { 348 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); 349 } 350 } 351 352 static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, 353 tcg_target_long offset) 354 { 355 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); 356 } 357 358 static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, 359 tcg_target_long offset) 360 { 361 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); 362 } 363 364 static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, 365 tcg_target_long offset) 366 { 367 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); 368 } 369 370 static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, 371 tcg_target_long offset) 372 { 373 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); 374 } 375 376 static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, 377 tcg_target_long offset) 378 { 379 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); 380 } 381 382 static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, 383 tcg_target_long offset) 384 { 385 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); 386 } 387 388 static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, 389 tcg_target_long offset) 390 { 391 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); 392 } 393 394 static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, 395 tcg_target_long offset) 396 { 397 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); 398 } 399 400 static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 401 { 402 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); 403 } 404 405 static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 406 { 407 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); 408 } 409 410 static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 411 { 412 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); 413 } 414 415 static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 416 { 417 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); 418 } 419 420 static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 421 { 422 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); 423 } 424 425 static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 426 { 427 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); 428 } 429 430 static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 431 { 432 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); 433 } 434 435 static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 436 { 437 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); 438 } 439 440 static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 441 { 442 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); 443 } 444 445 static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) 446 { 447 if (TCG_TARGET_HAS_neg_i32) { 448 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); 449 } else { 450 tcg_gen_subfi_i32(ret, 0, arg); 451 } 452 } 453 454 static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) 455 { 456 if (TCG_TARGET_HAS_not_i32) { 457 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); 458 } else { 459 tcg_gen_xori_i32(ret, arg, -1); 460 } 461 } 462 463 /* 64 bit ops */ 464 465 void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); 466 void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 467 void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); 468 void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 469 void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 470 void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 471 void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 472 void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 473 void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 474 void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 475 void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 476 void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 477 void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 478 void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 479 void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 480 void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 481 void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 482 void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 483 void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 484 void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 485 void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 486 void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 487 void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); 488 void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); 489 void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); 490 void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2); 491 void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 492 void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 493 void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 494 void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 495 void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, 496 unsigned int ofs, unsigned int len); 497 void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, 498 unsigned int ofs, unsigned int len); 499 void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, 500 unsigned int ofs, unsigned int len); 501 void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, 502 unsigned int ofs, unsigned int len); 503 void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, 504 unsigned int ofs); 505 void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *); 506 void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *); 507 void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, 508 TCGv_i64 arg1, TCGv_i64 arg2); 509 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, 510 TCGv_i64 arg1, int64_t arg2); 511 void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, 512 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); 513 void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, 514 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); 515 void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, 516 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); 517 void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); 518 void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); 519 void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); 520 void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg); 521 void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg); 522 void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); 523 void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); 524 void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg); 525 void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg); 526 void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); 527 void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); 528 void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); 529 void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); 530 void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); 531 void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); 532 void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); 533 void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); 534 void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); 535 void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); 536 void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); 537 538 /* Replicate a value of size @vece from @in to all the lanes in @out */ 539 void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in); 540 541 #if TCG_TARGET_REG_BITS == 64 542 static inline void tcg_gen_discard_i64(TCGv_i64 arg) 543 { 544 tcg_gen_op1_i64(INDEX_op_discard, arg); 545 } 546 547 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) 548 { 549 if (ret != arg) { 550 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); 551 } 552 } 553 554 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, 555 tcg_target_long offset) 556 { 557 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); 558 } 559 560 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, 561 tcg_target_long offset) 562 { 563 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); 564 } 565 566 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, 567 tcg_target_long offset) 568 { 569 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); 570 } 571 572 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, 573 tcg_target_long offset) 574 { 575 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); 576 } 577 578 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, 579 tcg_target_long offset) 580 { 581 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); 582 } 583 584 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, 585 tcg_target_long offset) 586 { 587 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); 588 } 589 590 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, 591 tcg_target_long offset) 592 { 593 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); 594 } 595 596 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, 597 tcg_target_long offset) 598 { 599 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); 600 } 601 602 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, 603 tcg_target_long offset) 604 { 605 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); 606 } 607 608 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, 609 tcg_target_long offset) 610 { 611 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); 612 } 613 614 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, 615 tcg_target_long offset) 616 { 617 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); 618 } 619 620 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 621 { 622 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); 623 } 624 625 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 626 { 627 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); 628 } 629 630 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 631 { 632 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); 633 } 634 635 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 636 { 637 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); 638 } 639 640 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 641 { 642 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); 643 } 644 645 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 646 { 647 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); 648 } 649 650 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 651 { 652 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); 653 } 654 655 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 656 { 657 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); 658 } 659 660 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 661 { 662 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); 663 } 664 #else /* TCG_TARGET_REG_BITS == 32 */ 665 void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); 666 void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); 667 void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); 668 669 void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 670 void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 671 672 void tcg_gen_discard_i64(TCGv_i64 arg); 673 void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); 674 void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); 675 void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); 676 void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); 677 void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); 678 void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); 679 void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); 680 void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); 681 void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); 682 void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 683 void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 684 void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 685 void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 686 void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 687 void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 688 void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 689 #endif /* TCG_TARGET_REG_BITS */ 690 691 static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) 692 { 693 if (TCG_TARGET_HAS_neg_i64) { 694 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); 695 } else { 696 tcg_gen_subfi_i64(ret, 0, arg); 697 } 698 } 699 700 /* Size changing operations. */ 701 702 void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg); 703 void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg); 704 void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high); 705 void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg); 706 void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); 707 void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); 708 void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); 709 710 void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src); 711 void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg); 712 void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi); 713 714 static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) 715 { 716 tcg_gen_deposit_i64(ret, lo, hi, 32, 32); 717 } 718 719 /* QEMU specific operations. */ 720 721 #ifndef TARGET_LONG_BITS 722 #error must include QEMU headers 723 #endif 724 725 #if TARGET_INSN_START_WORDS == 1 726 # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 727 static inline void tcg_gen_insn_start(target_ulong pc) 728 { 729 tcg_gen_op1(INDEX_op_insn_start, pc); 730 } 731 # else 732 static inline void tcg_gen_insn_start(target_ulong pc) 733 { 734 tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32)); 735 } 736 # endif 737 #elif TARGET_INSN_START_WORDS == 2 738 # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 739 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) 740 { 741 tcg_gen_op2(INDEX_op_insn_start, pc, a1); 742 } 743 # else 744 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) 745 { 746 tcg_gen_op4(INDEX_op_insn_start, 747 (uint32_t)pc, (uint32_t)(pc >> 32), 748 (uint32_t)a1, (uint32_t)(a1 >> 32)); 749 } 750 # endif 751 #elif TARGET_INSN_START_WORDS == 3 752 # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 753 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, 754 target_ulong a2) 755 { 756 tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2); 757 } 758 # else 759 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, 760 target_ulong a2) 761 { 762 tcg_gen_op6(INDEX_op_insn_start, 763 (uint32_t)pc, (uint32_t)(pc >> 32), 764 (uint32_t)a1, (uint32_t)(a1 >> 32), 765 (uint32_t)a2, (uint32_t)(a2 >> 32)); 766 } 767 # endif 768 #else 769 # error "Unhandled number of operands to insn_start" 770 #endif 771 772 /** 773 * tcg_gen_exit_tb() - output exit_tb TCG operation 774 * @tb: The TranslationBlock from which we are exiting 775 * @idx: Direct jump slot index, or exit request 776 * 777 * See tcg/README for more info about this TCG operation. 778 * See also tcg.h and the block comment above TB_EXIT_MASK. 779 * 780 * For a normal exit from the TB, back to the main loop, @tb should 781 * be NULL and @idx should be 0. Otherwise, @tb should be valid and 782 * @idx should be one of the TB_EXIT_ values. 783 */ 784 void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx); 785 786 /** 787 * tcg_gen_goto_tb() - output goto_tb TCG operation 788 * @idx: Direct jump slot index (0 or 1) 789 * 790 * See tcg/README for more info about this TCG operation. 791 * 792 * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within 793 * the pages this TB resides in because we don't take care of direct jumps when 794 * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a 795 * static address translation, so the destination address is always valid, TBs 796 * are always invalidated properly, and direct jumps are reset when mapping 797 * changes. 798 */ 799 void tcg_gen_goto_tb(unsigned idx); 800 801 /** 802 * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid 803 * @addr: Guest address of the target TB 804 * 805 * If the TB is not valid, jump to the epilogue. 806 * 807 * This operation is optional. If the TCG backend does not implement goto_ptr, 808 * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument. 809 */ 810 void tcg_gen_lookup_and_goto_ptr(void); 811 812 static inline void tcg_gen_plugin_cb_start(unsigned from, unsigned type, 813 unsigned wr) 814 { 815 tcg_gen_op3(INDEX_op_plugin_cb_start, from, type, wr); 816 } 817 818 static inline void tcg_gen_plugin_cb_end(void) 819 { 820 tcg_emit_op(INDEX_op_plugin_cb_end, 0); 821 } 822 823 #if TARGET_LONG_BITS == 32 824 #define tcg_temp_new() tcg_temp_new_i32() 825 #define tcg_global_mem_new tcg_global_mem_new_i32 826 #define tcg_temp_free tcg_temp_free_i32 827 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 828 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 829 #else 830 #define tcg_temp_new() tcg_temp_new_i64() 831 #define tcg_global_mem_new tcg_global_mem_new_i64 832 #define tcg_temp_free tcg_temp_free_i64 833 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 834 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 835 #endif 836 837 void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp); 838 void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp); 839 void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp); 840 void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp); 841 void tcg_gen_qemu_ld_i128(TCGv_i128, TCGv, TCGArg, MemOp); 842 void tcg_gen_qemu_st_i128(TCGv_i128, TCGv, TCGArg, MemOp); 843 844 void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, 845 TCGArg, MemOp); 846 void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, 847 TCGArg, MemOp); 848 void tcg_gen_atomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, 849 TCGArg, MemOp); 850 851 void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, 852 TCGArg, MemOp); 853 void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, 854 TCGArg, MemOp); 855 void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, 856 TCGArg, MemOp); 857 858 void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 859 void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 860 861 void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 862 void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 863 void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 864 void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 865 void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 866 void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 867 void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 868 void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 869 void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 870 void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 871 void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 872 void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 873 void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 874 void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 875 void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 876 void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 877 878 void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 879 void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 880 void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 881 void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 882 void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 883 void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 884 void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 885 void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 886 void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 887 void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 888 void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 889 void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 890 void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 891 void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 892 void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 893 void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 894 895 void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); 896 void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); 897 void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); 898 void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_long); 899 void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t); 900 void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 901 void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 902 void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 903 void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 904 void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 905 void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 906 void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 907 void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 908 void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 909 void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 910 void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 911 void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a); 912 void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a); 913 void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a); 914 void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 915 void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 916 void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 917 void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 918 void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 919 void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 920 void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 921 void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 922 923 void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); 924 void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); 925 void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); 926 void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); 927 void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); 928 929 void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); 930 void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); 931 void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); 932 void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); 933 934 void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); 935 void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); 936 void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); 937 void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); 938 void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); 939 940 void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, 941 TCGv_vec a, TCGv_vec b); 942 943 void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, 944 TCGv_vec b, TCGv_vec c); 945 void tcg_gen_cmpsel_vec(TCGCond cond, unsigned vece, TCGv_vec r, 946 TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d); 947 948 void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); 949 void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); 950 void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); 951 952 #if TARGET_LONG_BITS == 64 953 #define tcg_gen_movi_tl tcg_gen_movi_i64 954 #define tcg_gen_mov_tl tcg_gen_mov_i64 955 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 956 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 957 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 958 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 959 #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 960 #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 961 #define tcg_gen_ld_tl tcg_gen_ld_i64 962 #define tcg_gen_st8_tl tcg_gen_st8_i64 963 #define tcg_gen_st16_tl tcg_gen_st16_i64 964 #define tcg_gen_st32_tl tcg_gen_st32_i64 965 #define tcg_gen_st_tl tcg_gen_st_i64 966 #define tcg_gen_add_tl tcg_gen_add_i64 967 #define tcg_gen_addi_tl tcg_gen_addi_i64 968 #define tcg_gen_sub_tl tcg_gen_sub_i64 969 #define tcg_gen_neg_tl tcg_gen_neg_i64 970 #define tcg_gen_abs_tl tcg_gen_abs_i64 971 #define tcg_gen_subfi_tl tcg_gen_subfi_i64 972 #define tcg_gen_subi_tl tcg_gen_subi_i64 973 #define tcg_gen_and_tl tcg_gen_and_i64 974 #define tcg_gen_andi_tl tcg_gen_andi_i64 975 #define tcg_gen_or_tl tcg_gen_or_i64 976 #define tcg_gen_ori_tl tcg_gen_ori_i64 977 #define tcg_gen_xor_tl tcg_gen_xor_i64 978 #define tcg_gen_xori_tl tcg_gen_xori_i64 979 #define tcg_gen_not_tl tcg_gen_not_i64 980 #define tcg_gen_shl_tl tcg_gen_shl_i64 981 #define tcg_gen_shli_tl tcg_gen_shli_i64 982 #define tcg_gen_shr_tl tcg_gen_shr_i64 983 #define tcg_gen_shri_tl tcg_gen_shri_i64 984 #define tcg_gen_sar_tl tcg_gen_sar_i64 985 #define tcg_gen_sari_tl tcg_gen_sari_i64 986 #define tcg_gen_brcond_tl tcg_gen_brcond_i64 987 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 988 #define tcg_gen_setcond_tl tcg_gen_setcond_i64 989 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 990 #define tcg_gen_mul_tl tcg_gen_mul_i64 991 #define tcg_gen_muli_tl tcg_gen_muli_i64 992 #define tcg_gen_div_tl tcg_gen_div_i64 993 #define tcg_gen_rem_tl tcg_gen_rem_i64 994 #define tcg_gen_divu_tl tcg_gen_divu_i64 995 #define tcg_gen_remu_tl tcg_gen_remu_i64 996 #define tcg_gen_discard_tl tcg_gen_discard_i64 997 #define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32 998 #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 999 #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 1000 #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 1001 #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 1002 #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 1003 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 1004 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 1005 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 1006 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 1007 #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 1008 #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 1009 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 1010 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 1011 #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 1012 #define tcg_gen_bswap_tl tcg_gen_bswap64_i64 1013 #define tcg_gen_hswap_tl tcg_gen_hswap_i64 1014 #define tcg_gen_wswap_tl tcg_gen_wswap_i64 1015 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 1016 #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64 1017 #define tcg_gen_andc_tl tcg_gen_andc_i64 1018 #define tcg_gen_eqv_tl tcg_gen_eqv_i64 1019 #define tcg_gen_nand_tl tcg_gen_nand_i64 1020 #define tcg_gen_nor_tl tcg_gen_nor_i64 1021 #define tcg_gen_orc_tl tcg_gen_orc_i64 1022 #define tcg_gen_clz_tl tcg_gen_clz_i64 1023 #define tcg_gen_ctz_tl tcg_gen_ctz_i64 1024 #define tcg_gen_clzi_tl tcg_gen_clzi_i64 1025 #define tcg_gen_ctzi_tl tcg_gen_ctzi_i64 1026 #define tcg_gen_clrsb_tl tcg_gen_clrsb_i64 1027 #define tcg_gen_ctpop_tl tcg_gen_ctpop_i64 1028 #define tcg_gen_rotl_tl tcg_gen_rotl_i64 1029 #define tcg_gen_rotli_tl tcg_gen_rotli_i64 1030 #define tcg_gen_rotr_tl tcg_gen_rotr_i64 1031 #define tcg_gen_rotri_tl tcg_gen_rotri_i64 1032 #define tcg_gen_deposit_tl tcg_gen_deposit_i64 1033 #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64 1034 #define tcg_gen_extract_tl tcg_gen_extract_i64 1035 #define tcg_gen_sextract_tl tcg_gen_sextract_i64 1036 #define tcg_gen_extract2_tl tcg_gen_extract2_i64 1037 #define tcg_constant_tl tcg_constant_i64 1038 #define tcg_gen_movcond_tl tcg_gen_movcond_i64 1039 #define tcg_gen_add2_tl tcg_gen_add2_i64 1040 #define tcg_gen_sub2_tl tcg_gen_sub2_i64 1041 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 1042 #define tcg_gen_muls2_tl tcg_gen_muls2_i64 1043 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 1044 #define tcg_gen_smin_tl tcg_gen_smin_i64 1045 #define tcg_gen_umin_tl tcg_gen_umin_i64 1046 #define tcg_gen_smax_tl tcg_gen_smax_i64 1047 #define tcg_gen_umax_tl tcg_gen_umax_i64 1048 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 1049 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 1050 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 1051 #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64 1052 #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64 1053 #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64 1054 #define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i64 1055 #define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i64 1056 #define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i64 1057 #define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i64 1058 #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64 1059 #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64 1060 #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64 1061 #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64 1062 #define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i64 1063 #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64 1064 #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64 1065 #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64 1066 #define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec 1067 #define tcg_gen_dup_tl tcg_gen_dup_i64 1068 #else 1069 #define tcg_gen_movi_tl tcg_gen_movi_i32 1070 #define tcg_gen_mov_tl tcg_gen_mov_i32 1071 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 1072 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 1073 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 1074 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 1075 #define tcg_gen_ld32u_tl tcg_gen_ld_i32 1076 #define tcg_gen_ld32s_tl tcg_gen_ld_i32 1077 #define tcg_gen_ld_tl tcg_gen_ld_i32 1078 #define tcg_gen_st8_tl tcg_gen_st8_i32 1079 #define tcg_gen_st16_tl tcg_gen_st16_i32 1080 #define tcg_gen_st32_tl tcg_gen_st_i32 1081 #define tcg_gen_st_tl tcg_gen_st_i32 1082 #define tcg_gen_add_tl tcg_gen_add_i32 1083 #define tcg_gen_addi_tl tcg_gen_addi_i32 1084 #define tcg_gen_sub_tl tcg_gen_sub_i32 1085 #define tcg_gen_neg_tl tcg_gen_neg_i32 1086 #define tcg_gen_abs_tl tcg_gen_abs_i32 1087 #define tcg_gen_subfi_tl tcg_gen_subfi_i32 1088 #define tcg_gen_subi_tl tcg_gen_subi_i32 1089 #define tcg_gen_and_tl tcg_gen_and_i32 1090 #define tcg_gen_andi_tl tcg_gen_andi_i32 1091 #define tcg_gen_or_tl tcg_gen_or_i32 1092 #define tcg_gen_ori_tl tcg_gen_ori_i32 1093 #define tcg_gen_xor_tl tcg_gen_xor_i32 1094 #define tcg_gen_xori_tl tcg_gen_xori_i32 1095 #define tcg_gen_not_tl tcg_gen_not_i32 1096 #define tcg_gen_shl_tl tcg_gen_shl_i32 1097 #define tcg_gen_shli_tl tcg_gen_shli_i32 1098 #define tcg_gen_shr_tl tcg_gen_shr_i32 1099 #define tcg_gen_shri_tl tcg_gen_shri_i32 1100 #define tcg_gen_sar_tl tcg_gen_sar_i32 1101 #define tcg_gen_sari_tl tcg_gen_sari_i32 1102 #define tcg_gen_brcond_tl tcg_gen_brcond_i32 1103 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 1104 #define tcg_gen_setcond_tl tcg_gen_setcond_i32 1105 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 1106 #define tcg_gen_mul_tl tcg_gen_mul_i32 1107 #define tcg_gen_muli_tl tcg_gen_muli_i32 1108 #define tcg_gen_div_tl tcg_gen_div_i32 1109 #define tcg_gen_rem_tl tcg_gen_rem_i32 1110 #define tcg_gen_divu_tl tcg_gen_divu_i32 1111 #define tcg_gen_remu_tl tcg_gen_remu_i32 1112 #define tcg_gen_discard_tl tcg_gen_discard_i32 1113 #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 1114 #define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32 1115 #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 1116 #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 1117 #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 1118 #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 1119 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 1120 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 1121 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 1122 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 1123 #define tcg_gen_ext32u_tl tcg_gen_mov_i32 1124 #define tcg_gen_ext32s_tl tcg_gen_mov_i32 1125 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 1126 #define tcg_gen_bswap32_tl(D, S, F) tcg_gen_bswap32_i32(D, S) 1127 #define tcg_gen_bswap_tl tcg_gen_bswap32_i32 1128 #define tcg_gen_hswap_tl tcg_gen_hswap_i32 1129 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 1130 #define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32 1131 #define tcg_gen_andc_tl tcg_gen_andc_i32 1132 #define tcg_gen_eqv_tl tcg_gen_eqv_i32 1133 #define tcg_gen_nand_tl tcg_gen_nand_i32 1134 #define tcg_gen_nor_tl tcg_gen_nor_i32 1135 #define tcg_gen_orc_tl tcg_gen_orc_i32 1136 #define tcg_gen_clz_tl tcg_gen_clz_i32 1137 #define tcg_gen_ctz_tl tcg_gen_ctz_i32 1138 #define tcg_gen_clzi_tl tcg_gen_clzi_i32 1139 #define tcg_gen_ctzi_tl tcg_gen_ctzi_i32 1140 #define tcg_gen_clrsb_tl tcg_gen_clrsb_i32 1141 #define tcg_gen_ctpop_tl tcg_gen_ctpop_i32 1142 #define tcg_gen_rotl_tl tcg_gen_rotl_i32 1143 #define tcg_gen_rotli_tl tcg_gen_rotli_i32 1144 #define tcg_gen_rotr_tl tcg_gen_rotr_i32 1145 #define tcg_gen_rotri_tl tcg_gen_rotri_i32 1146 #define tcg_gen_deposit_tl tcg_gen_deposit_i32 1147 #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32 1148 #define tcg_gen_extract_tl tcg_gen_extract_i32 1149 #define tcg_gen_sextract_tl tcg_gen_sextract_i32 1150 #define tcg_gen_extract2_tl tcg_gen_extract2_i32 1151 #define tcg_constant_tl tcg_constant_i32 1152 #define tcg_gen_movcond_tl tcg_gen_movcond_i32 1153 #define tcg_gen_add2_tl tcg_gen_add2_i32 1154 #define tcg_gen_sub2_tl tcg_gen_sub2_i32 1155 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 1156 #define tcg_gen_muls2_tl tcg_gen_muls2_i32 1157 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 1158 #define tcg_gen_smin_tl tcg_gen_smin_i32 1159 #define tcg_gen_umin_tl tcg_gen_umin_i32 1160 #define tcg_gen_smax_tl tcg_gen_smax_i32 1161 #define tcg_gen_umax_tl tcg_gen_umax_i32 1162 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 1163 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 1164 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 1165 #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32 1166 #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32 1167 #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32 1168 #define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i32 1169 #define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i32 1170 #define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i32 1171 #define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i32 1172 #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32 1173 #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32 1174 #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32 1175 #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32 1176 #define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i32 1177 #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32 1178 #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32 1179 #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32 1180 #define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec 1181 #define tcg_gen_dup_tl tcg_gen_dup_i32 1182 #endif 1183 1184 #if UINTPTR_MAX == UINT32_MAX 1185 # define PTR i32 1186 # define NAT TCGv_i32 1187 #else 1188 # define PTR i64 1189 # define NAT TCGv_i64 1190 #endif 1191 1192 static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) 1193 { 1194 glue(tcg_gen_ld_,PTR)((NAT)r, a, o); 1195 } 1196 1197 static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) 1198 { 1199 glue(tcg_gen_st_, PTR)((NAT)r, a, o); 1200 } 1201 1202 static inline void tcg_gen_discard_ptr(TCGv_ptr a) 1203 { 1204 glue(tcg_gen_discard_,PTR)((NAT)a); 1205 } 1206 1207 static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b) 1208 { 1209 glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b); 1210 } 1211 1212 static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b) 1213 { 1214 glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b); 1215 } 1216 1217 static inline void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s) 1218 { 1219 glue(tcg_gen_mov_,PTR)((NAT)d, (NAT)s); 1220 } 1221 1222 static inline void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s) 1223 { 1224 glue(tcg_gen_movi_,PTR)((NAT)d, s); 1225 } 1226 1227 static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a, 1228 intptr_t b, TCGLabel *label) 1229 { 1230 glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label); 1231 } 1232 1233 static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a) 1234 { 1235 #if UINTPTR_MAX == UINT32_MAX 1236 tcg_gen_mov_i32((NAT)r, a); 1237 #else 1238 tcg_gen_ext_i32_i64((NAT)r, a); 1239 #endif 1240 } 1241 1242 static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a) 1243 { 1244 #if UINTPTR_MAX == UINT32_MAX 1245 tcg_gen_extrl_i64_i32((NAT)r, a); 1246 #else 1247 tcg_gen_mov_i64((NAT)r, a); 1248 #endif 1249 } 1250 1251 static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a) 1252 { 1253 #if UINTPTR_MAX == UINT32_MAX 1254 tcg_gen_extu_i32_i64(r, (NAT)a); 1255 #else 1256 tcg_gen_mov_i64(r, (NAT)a); 1257 #endif 1258 } 1259 1260 static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a) 1261 { 1262 #if UINTPTR_MAX == UINT32_MAX 1263 tcg_gen_mov_i32(r, (NAT)a); 1264 #else 1265 tcg_gen_extrl_i64_i32(r, (NAT)a); 1266 #endif 1267 } 1268 1269 #undef PTR 1270 #undef NAT 1271 1272 #endif /* TCG_TCG_OP_H */ 1273